| Message ID | 1476702719-10337-1-git-send-email-yamada.masahiro@socionext.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Mon, Oct 17, 2016 at 08:11:59PM +0900, Masahiro Yamada wrote: > Socionext LD11 SoC (arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi) > needs to handle 4 reset lines for EHCI. Why? What makes it different from other EHCI implementations? thanks, greg k-h
Hi Greg, 2016-10-17 21:30 GMT+09:00 Greg Kroah-Hartman <gregkh@linuxfoundation.org>: > On Mon, Oct 17, 2016 at 08:11:59PM +0900, Masahiro Yamada wrote: >> Socionext LD11 SoC (arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi) >> needs to handle 4 reset lines for EHCI. > > Why? What makes it different from other EHCI implementations? > > thanks, > > greg k-h This is a generic EHCI driver, but the number of clocks/resets are SoC-specific. The following patch you picked up will remind you something? commit 73577d61799e8d8bb7d69a9acdc54923e5998138 Author: Icenowy Zheng <icenowy@aosc.xyz> Date: Fri Aug 12 11:06:22 2016 +0800 ehci-platform: add the max clock number to 4 Allwinner A64 EHCI requires 4 clocks to be enabled. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Acked-by: Alan Stern <stern@rowland.harvard.edu> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
diff --git a/drivers/usb/host/ehci-platform.c b/drivers/usb/host/ehci-platform.c index 876dca4..a268d9e 100644 --- a/drivers/usb/host/ehci-platform.c +++ b/drivers/usb/host/ehci-platform.c @@ -39,7 +39,7 @@ #define DRIVER_DESC "EHCI generic platform driver" #define EHCI_MAX_CLKS 4 -#define EHCI_MAX_RSTS 3 +#define EHCI_MAX_RSTS 4 #define hcd_to_ehci_priv(h) ((struct ehci_platform_priv *)hcd_to_ehci(h)->priv) struct ehci_platform_priv {
Socionext LD11 SoC (arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi) needs to handle 4 reset lines for EHCI. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> --- drivers/usb/host/ehci-platform.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)