From patchwork Wed Oct 19 10:08:22 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 9383769 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 88F4860487 for ; Wed, 19 Oct 2016 10:11:15 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7A2B929903 for ; Wed, 19 Oct 2016 10:11:15 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6DE7629909; Wed, 19 Oct 2016 10:11:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED, T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 660C229903 for ; Wed, 19 Oct 2016 10:11:14 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1bwnoo-0005bq-2a; Wed, 19 Oct 2016 10:09:54 +0000 Received: from mail-wm0-x233.google.com ([2a00:1450:400c:c09::233]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1bwnoG-0005IC-Uj for linux-arm-kernel@lists.infradead.org; Wed, 19 Oct 2016 10:09:23 +0000 Received: by mail-wm0-x233.google.com with SMTP id z189so41363742wmb.1 for ; Wed, 19 Oct 2016 03:08:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fBWabavvH7x6Mbb5skvbv3gKbAPTkko2JHQsc4XYyk0=; b=nY59YTJbJnm44XpCN2MZAC2Ai5NOhBzitmHXbYqIeVYX0sXiLDXgSFQEJmVQWM9NQx NSvxJmVEGgNCY7aikXxACZuVkTn9m3NBZNKCBzCH0gZCzjc4lN8t/vgtPBpYXbAtHzYX 3l7nJH+RRQTBKGdge3p/3h3Zb8rxW2v8Px9H/GzlvY2kSkY52YBhbJawuyAIobH12Rln eiJagrm5FH8TKFB0tEQviyzKldmUYAGJrmtOnD7ad/remW+YT+0gBXgum3sHVHMi/7KQ eFZB8dwyTFeFg5EdymhpOsZqqXA4XYT04o0V4aSd2a4vKys4Npw3YjEPoMU4IVV5xPpA edNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fBWabavvH7x6Mbb5skvbv3gKbAPTkko2JHQsc4XYyk0=; b=j+dkDa7rMmJGg1Ky6X8ao/NfHZfjmcX4XxjcaQTIHFrSPkVc3K6s9FCbvWxoa4rtSi R3PFvUqMQxCIXfA6YfaAWOdt+YYhILXGfoLTdmzcMI5k2HTiZxhmU0OiOaoUZx0cUjS7 Y846eoYbRpO75XGPeHVG0nYf/eHIFzoEmUCudNi0qObB2KrMuA5bkNnlk0wS+6CCheJK DyzfwhsS1IZUzIrfArt8IwdjsTEKF4fCo8A10fLlS5joIgPtTnOfVVXzkKkyTgnT/bqs BZEbOqzw8wWgmrk4Glv4IOEP2h4/d00Wvyvc3P48/v14d8Vuc7PWLLExX11p0qi850hG of2g== X-Gm-Message-State: AA6/9RlKo3jJPQU4D1d1wfuFxdLbPWsPGX9GOP7FmrUIr/SEy2H3cPG9RCdTWa+gawIjJIJ8 X-Received: by 10.28.125.67 with SMTP id y64mr4920576wmc.65.1476871736712; Wed, 19 Oct 2016 03:08:56 -0700 (PDT) Received: from boomer.baylibre.com ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id l15sm4199066wmd.7.2016.10.19.03.08.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 19 Oct 2016 03:08:56 -0700 (PDT) From: Jerome Brunet To: Carlo Caione , Kevin Hilman , Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring Subject: [PATCH 2/9] dt-bindings: interrupt-controller: add DT binding for meson GPIO interrupt controller Date: Wed, 19 Oct 2016 12:08:22 +0200 Message-Id: <1476871709-8359-3-git-send-email-jbrunet@baylibre.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1476871709-8359-1-git-send-email-jbrunet@baylibre.com> References: <1476871709-8359-1-git-send-email-jbrunet@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20161019_030921_286006_933797C9 X-CRM114-Status: GOOD ( 16.72 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Catalin Marinas , Linus Walleij , Will Deacon , linux-kernel@vger.kernel.org, Russell King , linux-gpio@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Jerome Brunet Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This commit adds the device tree bindings description for Amlogic's GPIO interrupt controller available on the meson8, meson8b and gxbb SoC families Signed-off-by: Jerome Brunet --- Rob, I did not include the Ack you gave for the RFC as bindings have slightly changed. Only the interrupt property has be removed following a discussion I had with Marc. .../amlogic,meson-gpio-intc.txt | 31 ++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt diff --git a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt new file mode 100644 index 000000000000..2464d9a0865d --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt @@ -0,0 +1,31 @@ +Amlogic meson GPIO interrupt controller + +Meson SoCs contains an interrupt controller which is able watch the SoC pads +and generate an interrupt on edges or level. The controller is essentially a +256 pads to 8 GIC interrupt multiplexer, with a filter block to select edge +or level and polarity. We don’t expose all 256 mux inputs because the +documentation shows that upper part is not mapped to any pad. The actual number +of interrupt exposed depends on the SoC. + +Required properties: + +- compatible : should be either + "amlogic,meson8-gpio-intc” for meson8 SoCs (AML7826MX) or + “amlogic,meson8b-gpio-intc” for meson8b SoCs (S805) or + “amlogic,meson-gxbb-gpio-intc” for GXBB SoCs (S905) +- interrupt-parent : a phandle to the GIC the interrupts are routed to. + Usually this is provided at the root level of the device tree as it is + common to most of the SoC +- reg : Specifies base physical address and size of the registers. +- interrupt-controller : Identifies the node as an interrupt controller. +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The value must be 2. + +Example: + +gpio_interrupt: interrupt-controller@9880 { + compatible = "amlogic,meson-gxbb-gpio-intc"; + reg = <0x0 0x9880 0x0 0x10>; + interrupt-controller; + #interrupt-cells = <2>; +};