| Message ID | 1478264794-14652-4-git-send-email-dingtianhong@huawei.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi index bf322ed..f815d94 100644 --- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi @@ -281,6 +281,7 @@ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + hisilicon,erratum-161601; }; pmu { diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi index 5927bc4..d63990b 100644 --- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi @@ -260,6 +260,7 @@ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + hisilicon,erratum-161601; }; pmu {
Enable workaround for hisilicon erratum 161601 on Hip05-d02 and Hip06-d03 board. Signed-off-by: Ding Tianhong <dingtianhong@huawei.com> --- arch/arm64/boot/dts/hisilicon/hip05.dtsi | 1 + arch/arm64/boot/dts/hisilicon/hip06.dtsi | 1 + 2 files changed, 2 insertions(+)