From patchwork Fri Nov 4 15:51:22 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 9412753 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id C77FD60573 for ; Fri, 4 Nov 2016 15:53:50 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B7B6C2B162 for ; Fri, 4 Nov 2016 15:53:50 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A9E012B183; Fri, 4 Nov 2016 15:53:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED, T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 182802B162 for ; Fri, 4 Nov 2016 15:53:50 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1c2gmv-0004gA-0m; Fri, 04 Nov 2016 15:52:17 +0000 Received: from mail-wm0-x233.google.com ([2a00:1450:400c:c09::233]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1c2gmW-0003tY-2c for linux-arm-kernel@lists.infradead.org; Fri, 04 Nov 2016 15:51:57 +0000 Received: by mail-wm0-x233.google.com with SMTP id n67so58288570wme.1 for ; Fri, 04 Nov 2016 08:51:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=bTYCaRbLmEstES6oI83Eg9wkppY90kTNlXPAG3NSb9Q=; b=FNEWJ4vDpw1HdYCFra8+g1/rcL9gMW8s+6pjjPdNvWoK9FSFpMtOXaJ1tThZIa/2Jv gJCOPWoRCllyeTifFGuUn43itnozXQkXwfoPlJaHk3hlZnZDzB1b5QXFfkK8If5AkPsp 89pf5t5vySwi9hLSjbCNphSBzvY/XlOPHGLB2szPqfDwFFPQWYtjG8tx0BwjkiND8aC7 cpS5c5HwSXKbrsEcmF7hcV8YgwwDq0vFm6K5NgT2rKBF02H6g+uIkLxTtImNZN/+4/ak jqwET1kpJh2RhFRXv787UifhGU1QU/RLOVuWSuRt17isTECA5H+p1CsZFOMvIURhpdas 2y/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=bTYCaRbLmEstES6oI83Eg9wkppY90kTNlXPAG3NSb9Q=; b=JDlgKU+h9KELv/Nwdo2FxMjohPjrePpiT5kbpXWaIcPrR2sMuCTScRzBUBmBSWCEI/ Vnle4Rxb0K4pgPDNsvQp8DcuRfm3Pvdq2LOcagD6r5qOoU7tdlauVkvPXpkukMrK8/kt TnIQxM/E2Wg/90SBopkbmR9oW9PLXhfH8c5DFVAwlHycRZRcUkpG6XFfRON/B4p4qz4d 8LYptd0U4SBt4nJuk7wSzwA9+EpCInX1A5XnRI8f/CYH3ubQ4s44K/Nf8eotNKLP9XE4 c6fBvbALDr+6LGHWo3kyYtdZK2vwA+gxg8R3n6jNrSZIaf/4UDfhxVRfiMQF8q718i1e gT5g== X-Gm-Message-State: ABUngve+yTCGG8g2IHnxIL58fsHyh/XCykK5K4Pf0P91k3hmIwQg985ieS2jzAgB+/M1FdBA X-Received: by 10.28.13.144 with SMTP id 138mr4393594wmn.41.1478274689502; Fri, 04 Nov 2016 08:51:29 -0700 (PDT) Received: from localhost.localdomain ([90.63.244.31]) by smtp.gmail.com with ESMTPSA id n6sm14890685wjg.30.2016.11.04.08.51.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 04 Nov 2016 08:51:29 -0700 (PDT) From: Neil Armstrong To: f.fainelli@gmail.com, carlo@caione.org, khilman@baylibre.com, andrew@lunn.ch Subject: [PATCH net-next 1/2] net: mdio-mux-mmioreg: Add support for 16bit and 32bit register sizes Date: Fri, 4 Nov 2016 16:51:22 +0100 Message-Id: <1478274683-1503-2-git-send-email-narmstrong@baylibre.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1478274683-1503-1-git-send-email-narmstrong@baylibre.com> References: <1478274683-1503-1-git-send-email-narmstrong@baylibre.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20161104_085152_382098_C131AC5C X-CRM114-Status: GOOD ( 17.65 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: netdev@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Neil Armstrong MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP In order to support PHY switching on Amlogic GXL SoCs, add support for 16bit and 32bit registers sizes. Reviewed-by: Andrew Lunn Signed-off-by: Neil Armstrong Reviewed-by: Florian Fainelli --- .../devicetree/bindings/net/mdio-mux-mmioreg.txt | 4 +- drivers/net/phy/mdio-mux-mmioreg.c | 60 +++++++++++++++++----- 2 files changed, 49 insertions(+), 15 deletions(-) diff --git a/Documentation/devicetree/bindings/net/mdio-mux-mmioreg.txt b/Documentation/devicetree/bindings/net/mdio-mux-mmioreg.txt index 8516929..065e8bd 100644 --- a/Documentation/devicetree/bindings/net/mdio-mux-mmioreg.txt +++ b/Documentation/devicetree/bindings/net/mdio-mux-mmioreg.txt @@ -3,7 +3,7 @@ Properties for an MDIO bus multiplexer controlled by a memory-mapped device This is a special case of a MDIO bus multiplexer. A memory-mapped device, like an FPGA, is used to control which child bus is connected. The mdio-mux node must be a child of the memory-mapped device. The driver currently only -supports devices with eight-bit registers. +supports devices with 8, 16 or 32-bit registers. Required properties in addition to the generic multiplexer properties: @@ -11,7 +11,7 @@ Required properties in addition to the generic multiplexer properties: - reg : integer, contains the offset of the register that controls the bus multiplexer. The size field in the 'reg' property is the size of - register, and must therefore be 1. + register, and must therefore be 1, 2, or 4. - mux-mask : integer, contains an eight-bit mask that specifies which bits in the register control the actual bus multiplexer. The diff --git a/drivers/net/phy/mdio-mux-mmioreg.c b/drivers/net/phy/mdio-mux-mmioreg.c index d0bed52..6a33646 100644 --- a/drivers/net/phy/mdio-mux-mmioreg.c +++ b/drivers/net/phy/mdio-mux-mmioreg.c @@ -21,7 +21,8 @@ struct mdio_mux_mmioreg_state { void *mux_handle; phys_addr_t phys; - uint8_t mask; + unsigned int iosize; + unsigned int mask; }; /* @@ -47,17 +48,47 @@ static int mdio_mux_mmioreg_switch_fn(int current_child, int desired_child, struct mdio_mux_mmioreg_state *s = data; if (current_child ^ desired_child) { - void __iomem *p = ioremap(s->phys, 1); - uint8_t x, y; - + void __iomem *p = ioremap(s->phys, s->iosize); if (!p) return -ENOMEM; - x = ioread8(p); - y = (x & ~s->mask) | desired_child; - if (x != y) { - iowrite8((x & ~s->mask) | desired_child, p); - pr_debug("%s: %02x -> %02x\n", __func__, x, y); + switch (s->iosize) { + case sizeof(uint8_t): { + uint8_t x, y; + + x = ioread8(p); + y = (x & ~s->mask) | desired_child; + if (x != y) { + iowrite8((x & ~s->mask) | desired_child, p); + pr_debug("%s: %02x -> %02x\n", __func__, x, y); + } + + break; + } + case sizeof(uint16_t): { + uint16_t x, y; + + x = ioread16(p); + y = (x & ~s->mask) | desired_child; + if (x != y) { + iowrite16((x & ~s->mask) | desired_child, p); + pr_debug("%s: %04x -> %04x\n", __func__, x, y); + } + + break; + } + case sizeof(uint32_t): { + uint32_t x, y; + + x = ioread32(p); + y = (x & ~s->mask) | desired_child; + if (x != y) { + iowrite32((x & ~s->mask) | desired_child, p); + pr_debug("%s: %08x -> %08x\n", __func__, x, y); + } + + break; + } } iounmap(p); @@ -88,8 +119,11 @@ static int mdio_mux_mmioreg_probe(struct platform_device *pdev) } s->phys = res.start; - if (resource_size(&res) != sizeof(uint8_t)) { - dev_err(&pdev->dev, "only 8-bit registers are supported\n"); + s->iosize = resource_size(&res); + if (s->iosize != sizeof(uint8_t) && + s->iosize != sizeof(uint16_t) && + s->iosize != sizeof(uint32_t)) { + dev_err(&pdev->dev, "only 8/16/32-bit registers are supported\n"); return -EINVAL; } @@ -98,8 +132,8 @@ static int mdio_mux_mmioreg_probe(struct platform_device *pdev) dev_err(&pdev->dev, "missing or invalid mux-mask property\n"); return -ENODEV; } - if (be32_to_cpup(iprop) > 255) { - dev_err(&pdev->dev, "only 8-bit registers are supported\n"); + if (be32_to_cpup(iprop) >= BIT(s->iosize * 8)) { + dev_err(&pdev->dev, "only 8/16/32-bit registers are supported\n"); return -EINVAL; } s->mask = be32_to_cpup(iprop);