From patchwork Mon Nov 7 08:30:05 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mirza Krak X-Patchwork-Id: 9414467 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id BF34160512 for ; Mon, 7 Nov 2016 08:33:43 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AC6BD28C0C for ; Mon, 7 Nov 2016 08:33:43 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9EEB628C76; Mon, 7 Nov 2016 08:33:43 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED,FREEMAIL_FROM,RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 0BB2228C0C for ; Mon, 7 Nov 2016 08:33:42 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1c3fLg-0005d9-En; Mon, 07 Nov 2016 08:32:12 +0000 Received: from mail-lf0-x244.google.com ([2a00:1450:4010:c07::244]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1c3fKC-0004T1-J1 for linux-arm-kernel@lists.infradead.org; Mon, 07 Nov 2016 08:30:44 +0000 Received: by mail-lf0-x244.google.com with SMTP id o141so7439768lff.1 for ; Mon, 07 Nov 2016 00:30:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=mlU0LcNK7lNZz9pL4Aq0S0AzXvATpvZazn+AM95N1jg=; b=bV+SUlbmeGB/9SPmz4/xTaD3r91b/Js4Eb268lVf5+8HCVaURx/72TogciF/iWxxmO 8dVQqwXPIDZ0EUqKtgIwH+sBsQY3R6aPyALKQ+++nG17yH/xeAJw5mUM0u0nMulL/6F/ TIeKMsLkDKnK3m2wgNWFu1l4jQeXnROq4ytLN+o2EcrSgCTdYnAE58CcB3tDeIO+mOd5 LGfl3TaV6PRLmZ70wwwzhTt/o3IeWupogBBX2QIYLRJWqC7tpLJ7J3g09i/WilE/Q347 B2keAWqYrs8p4TjVkqgVi6NX+ZaL2c8usN96b7FKvcGDkaI+4Jy9+WwhP1BAew424am8 l1nQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=mlU0LcNK7lNZz9pL4Aq0S0AzXvATpvZazn+AM95N1jg=; b=gQRxCTD7iQXfr7d7sXIaRjtcT6hyyDiyWOVRxbuwHneCSRz73l0UlpZWWwDmVLfaqZ UNuOtJg9W2sENlYoO50G9zsa4DCchjFAv58+YyR+12BVBcoSBOfSTY8slLBZ6Faq++sk TNI10gZlshwQSyAMl6ryJyTGXiV//NSnngram/+46oF6lLX7iYzWAsoSDOZpU684jrAP JCtHVkeG96IO36QYGVaOqYiIvXrTOyFBYJFBK2B3pzmpZVekQpmpVgKOJmgbaa3P34aW BZRYAeziM3x7L/IKYY17ULAZmqxxfya27Kl7IKUFGHCq3K85GSvY/NN8IosNr4tvli24 oVIQ== X-Gm-Message-State: ABUngvfNxq0xcy3qlpCRJmOvKCSZKobcyGs8ilWSemHmat6b8QAMkCicyZsJ/VJ4e3no/A== X-Received: by 10.25.24.98 with SMTP id o95mr2661102lfi.4.1478507417829; Mon, 07 Nov 2016 00:30:17 -0800 (PST) Received: from mirza-hm.lan ([80.252.212.150]) by smtp.gmail.com with ESMTPSA id e15sm4928084lfg.32.2016.11.07.00.30.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Nov 2016 00:30:17 -0800 (PST) From: Mirza Krak X-Google-Original-From: Mirza Krak < mirza.krak@gmail.com > To: swarren@wwwdotorg.org, thierry.reding@gmail.com, jonathanh@nvidia.com Subject: [PATCH V4 6/6] bus: Add support for Tegra Generic Memory Interface Date: Mon, 7 Nov 2016 09:30:05 +0100 Message-Id: <1478507405-13204-7-git-send-email-mirza.krak@gmail.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1478507405-13204-1-git-send-email-mirza.krak@gmail.com> References: <1478507405-13204-1-git-send-email-mirza.krak@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20161107_003041_207499_144CCC1C X-CRM114-Status: GOOD ( 25.67 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, gnurou@gmail.com, pgaikwad@nvidia.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, pdeschrijver@nvidia.com, Mirza Krak , sboyd@codeaurora.org, linux@armlinux.org.uk, linux-kernel@vger.kernel.org, robh+dt@kernel.org, linux-tegra@vger.kernel.org, mturquette@baylibre.com, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Mirza Krak The Generic Memory Interface bus can be used to connect high-speed devices such as NOR flash, FPGAs, DSPs... Signed-off-by: Mirza Krak Tested-by: Marcel Ziswiler Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board Acked-by: Jon Hunter --- Changes in v2: - Fixed some checkpatch errors - Re-ordered probe to get rid of local variables - Moved of_platform_default_populate call to the end of probe - Use the timing and configuration properties from the child device - Added warning if more then 1 child device exist Changes in v3: - added helper function to disable the controller which is used in remove and on error. - Added logic to parse CS# from "ranges" property with fallback to "reg" property Changes in v4: - added sanity check of chip-select property (fail if invalid) - adjusted for device tree binding property name changes - fail probe if there are no child nodes - removed superfluous error message - removed superfluous newline in Kconfig drivers/bus/Kconfig | 7 ++ drivers/bus/Makefile | 1 + drivers/bus/tegra-gmi.c | 275 ++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 283 insertions(+) create mode 100644 drivers/bus/tegra-gmi.c -- 2.1.4 diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig index 4ed7d26..a9ebc4c 100644 --- a/drivers/bus/Kconfig +++ b/drivers/bus/Kconfig @@ -141,6 +141,13 @@ config TEGRA_ACONNECT Driver for the Tegra ACONNECT bus which is used to interface with the devices inside the Audio Processing Engine (APE) for Tegra210. +config TEGRA_GMI + tristate "Tegra Generic Memory Interface bus driver" + depends on ARCH_TEGRA + help + Driver for the Tegra Generic Memory Interface bus which can be used + to attach devices such as NOR, UART, FPGA and more. + config UNIPHIER_SYSTEM_BUS tristate "UniPhier System Bus driver" depends on ARCH_UNIPHIER && OF diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile index ac84cc4..34e2bab 100644 --- a/drivers/bus/Makefile +++ b/drivers/bus/Makefile @@ -18,5 +18,6 @@ obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o obj-$(CONFIG_SUNXI_RSB) += sunxi-rsb.o obj-$(CONFIG_SIMPLE_PM_BUS) += simple-pm-bus.o obj-$(CONFIG_TEGRA_ACONNECT) += tegra-aconnect.o +obj-$(CONFIG_TEGRA_GMI) += tegra-gmi.o obj-$(CONFIG_UNIPHIER_SYSTEM_BUS) += uniphier-system-bus.o obj-$(CONFIG_VEXPRESS_CONFIG) += vexpress-config.o diff --git a/drivers/bus/tegra-gmi.c b/drivers/bus/tegra-gmi.c new file mode 100644 index 0000000..687e212 --- /dev/null +++ b/drivers/bus/tegra-gmi.c @@ -0,0 +1,275 @@ +/* + * Driver for NVIDIA Generic Memory Interface + * + * Copyright (C) 2016 Host Mobility AB. All rights reserved. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ +#include +#include +#include +#include +#include +#include + +#define TEGRA_GMI_CONFIG 0x00 +#define TEGRA_GMI_CONFIG_GO BIT(31) +#define TEGRA_GMI_BUS_WIDTH_32BIT BIT(30) +#define TEGRA_GMI_MUX_MODE BIT(28) +#define TEGRA_GMI_RDY_BEFORE_DATA BIT(24) +#define TEGRA_GMI_RDY_ACTIVE_HIGH BIT(23) +#define TEGRA_GMI_ADV_ACTIVE_HIGH BIT(22) +#define TEGRA_GMI_OE_ACTIVE_HIGH BIT(21) +#define TEGRA_GMI_CS_ACTIVE_HIGH BIT(20) +#define TEGRA_GMI_CS_SELECT(x) ((x & 0x7) << 4) + +#define TEGRA_GMI_TIMING0 0x10 +#define TEGRA_GMI_MUXED_WIDTH(x) ((x & 0xf) << 12) +#define TEGRA_GMI_HOLD_WIDTH(x) ((x & 0xf) << 8) +#define TEGRA_GMI_ADV_WIDTH(x) ((x & 0xf) << 4) +#define TEGRA_GMI_CE_WIDTH(x) (x & 0xf) + +#define TEGRA_GMI_TIMING1 0x14 +#define TEGRA_GMI_WE_WIDTH(x) ((x & 0xff) << 16) +#define TEGRA_GMI_OE_WIDTH(x) ((x & 0xff) << 8) +#define TEGRA_GMI_WAIT_WIDTH(x) (x & 0xff) + +#define TEGRA_GMI_MAX_CHIP_SELECT 8 + +struct tegra_gmi_priv { + void __iomem *base; + struct reset_control *rst; + struct clk *clk; + + u32 snor_config; + u32 snor_timing0; + u32 snor_timing1; +}; + +static void tegra_gmi_disable(struct tegra_gmi_priv *priv) +{ + u32 config; + + /* stop GMI operation */ + config = readl(priv->base + TEGRA_GMI_CONFIG); + config &= ~TEGRA_GMI_CONFIG_GO; + writel(config, priv->base + TEGRA_GMI_CONFIG); + + reset_control_assert(priv->rst); + clk_disable_unprepare(priv->clk); +} + +static void tegra_gmi_init(struct device *dev, struct tegra_gmi_priv *priv) +{ + writel(priv->snor_timing0, priv->base + TEGRA_GMI_TIMING0); + writel(priv->snor_timing1, priv->base + TEGRA_GMI_TIMING1); + + priv->snor_config |= TEGRA_GMI_CONFIG_GO; + writel(priv->snor_config, priv->base + TEGRA_GMI_CONFIG); +} + +static int tegra_gmi_parse_dt(struct device *dev, struct tegra_gmi_priv *priv) +{ + struct device_node *child = of_get_next_available_child(dev->of_node, + NULL); + u32 property, ranges[4]; + int ret; + + if (!child) { + dev_err(dev, "no child nodes found\n"); + return -ENODEV; + } + + /* + * We currently only support one child device due to lack of + * chip-select address decoding. Which means that we only have one + * chip-select line from the GMI controller. + */ + if (of_get_child_count(dev->of_node) > 1) + dev_warn(dev, "only one child device is supported."); + + if (of_property_read_bool(child, "nvidia,snor-data-width-32bit")) + priv->snor_config |= TEGRA_GMI_BUS_WIDTH_32BIT; + + if (of_property_read_bool(child, "nvidia,snor-mux-mode")) + priv->snor_config |= TEGRA_GMI_MUX_MODE; + + if (of_property_read_bool(child, "nvidia,snor-rdy-active-before-data")) + priv->snor_config |= TEGRA_GMI_RDY_BEFORE_DATA; + + if (of_property_read_bool(child, "nvidia,snor-rdy-active-high")) + priv->snor_config |= TEGRA_GMI_RDY_ACTIVE_HIGH; + + if (of_property_read_bool(child, "nvidia,snor-adv-active-high")) + priv->snor_config |= TEGRA_GMI_ADV_ACTIVE_HIGH; + + if (of_property_read_bool(child, "nvidia,snor-oe-active-high")) + priv->snor_config |= TEGRA_GMI_OE_ACTIVE_HIGH; + + if (of_property_read_bool(child, "nvidia,snor-cs-active-high")) + priv->snor_config |= TEGRA_GMI_CS_ACTIVE_HIGH; + + /* Decode the CS# */ + ret = of_property_read_u32_array(child, "ranges", ranges, 4); + if (ret < 0) { + /* Invalid binding */ + if (ret == -EOVERFLOW) { + dev_err(dev, + "failed to decode CS: invalid ranges length\n"); + goto error_cs; + } + + /* + * If we reach here it means that the child node has an empty + * ranges or it does not exist at all. Attempt to decode the + * CS# from the reg property instead. + */ + ret = of_property_read_u32(child, "reg", &property); + if (ret < 0) { + dev_err(dev, + "failed to decode CS: no reg property found\n"); + goto error_cs; + } + } else { + property = ranges[1]; + } + + /* Valid chip selects are CS0-CS7 */ + if (property >= TEGRA_GMI_MAX_CHIP_SELECT) { + dev_err(dev, "invalid chip select: %d", property); + ret = -EINVAL; + goto error_cs; + } + + priv->snor_config |= TEGRA_GMI_CS_SELECT(property); + + /* The default values that are provided below are reset values */ + if (!of_property_read_u32(child, "nvidia,snor-muxed-width", &property)) + priv->snor_timing0 |= TEGRA_GMI_MUXED_WIDTH(property); + else + priv->snor_timing0 |= TEGRA_GMI_MUXED_WIDTH(1); + + if (!of_property_read_u32(child, "nvidia,snor-hold-width", &property)) + priv->snor_timing0 |= TEGRA_GMI_HOLD_WIDTH(property); + else + priv->snor_timing0 |= TEGRA_GMI_HOLD_WIDTH(1); + + if (!of_property_read_u32(child, "nvidia,snor-adv-width", &property)) + priv->snor_timing0 |= TEGRA_GMI_ADV_WIDTH(property); + else + priv->snor_timing0 |= TEGRA_GMI_ADV_WIDTH(1); + + if (!of_property_read_u32(child, "nvidia,snor-ce-width", &property)) + priv->snor_timing0 |= TEGRA_GMI_CE_WIDTH(property); + else + priv->snor_timing0 |= TEGRA_GMI_CE_WIDTH(4); + + if (!of_property_read_u32(child, "nvidia,snor-we-width", &property)) + priv->snor_timing1 |= TEGRA_GMI_WE_WIDTH(property); + else + priv->snor_timing1 |= TEGRA_GMI_WE_WIDTH(1); + + if (!of_property_read_u32(child, "nvidia,snor-oe-width", &property)) + priv->snor_timing1 |= TEGRA_GMI_OE_WIDTH(property); + else + priv->snor_timing1 |= TEGRA_GMI_OE_WIDTH(1); + + if (!of_property_read_u32(child, "nvidia,snor-wait-width", &property)) + priv->snor_timing1 |= TEGRA_GMI_WAIT_WIDTH(property); + else + priv->snor_timing1 |= TEGRA_GMI_WAIT_WIDTH(3); + +error_cs: + of_node_put(child); + return ret; +} + +static int tegra_gmi_probe(struct platform_device *pdev) +{ + struct resource *res; + struct device *dev = &pdev->dev; + struct tegra_gmi_priv *priv; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + priv->base = devm_ioremap_resource(dev, res); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + priv->clk = devm_clk_get(dev, "gmi"); + if (IS_ERR(priv->clk)) { + dev_err(dev, "can not get clock\n"); + return PTR_ERR(priv->clk); + } + + priv->rst = devm_reset_control_get(dev, "gmi"); + if (IS_ERR(priv->rst)) { + dev_err(dev, "can not get reset\n"); + return PTR_ERR(priv->rst); + } + + ret = tegra_gmi_parse_dt(dev, priv); + if (ret) + return ret; + + ret = clk_prepare_enable(priv->clk); + if (ret) { + dev_err(dev, "fail to enable clock.\n"); + return ret; + } + + reset_control_assert(priv->rst); + udelay(2); + reset_control_deassert(priv->rst); + + tegra_gmi_init(dev, priv); + + ret = of_platform_default_populate(dev->of_node, NULL, dev); + if (ret < 0) { + dev_err(dev, "fail to create devices.\n"); + tegra_gmi_disable(priv); + return ret; + } + + dev_set_drvdata(dev, priv); + + return 0; +} + +static int tegra_gmi_remove(struct platform_device *pdev) +{ + struct tegra_gmi_priv *priv = dev_get_drvdata(&pdev->dev); + + of_platform_depopulate(&pdev->dev); + + tegra_gmi_disable(priv); + + return 0; +} + +static const struct of_device_id tegra_gmi_id_table[] = { + { .compatible = "nvidia,tegra20-gmi", }, + { .compatible = "nvidia,tegra30-gmi", }, + { } +}; +MODULE_DEVICE_TABLE(of, tegra_gmi_id_table); + +static struct platform_driver tegra_gmi_driver = { + .probe = tegra_gmi_probe, + .remove = tegra_gmi_remove, + .driver = { + .name = "tegra-gmi", + .of_match_table = tegra_gmi_id_table, + }, +}; +module_platform_driver(tegra_gmi_driver); + +MODULE_AUTHOR("Mirza Krak