| Message ID | 1479106911-16049-2-git-send-email-wulf@rock-chips.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
William On Sun, Nov 13, 2016 at 11:01 PM, William Wu <wulf@rock-chips.com> wrote: > Since we needs to delay ~1ms to wait for 480MHz output clock > of USB2 PHY to become stable after turn on it, the delay time > is pretty long for something that's supposed to be "atomic" > like a clk_enable(). Consider that clk_enable() will disable > interrupt and that a 1ms interrupt latency is not sensible. > > The 480MHz output clock should be handled in prepare callbacks > which support gate a clk if the operation may sleep. > > Signed-off-by: William Wu <wulf@rock-chips.com> > --- > drivers/phy/phy-rockchip-inno-usb2.c | 12 ++++++------ > 1 file changed, 6 insertions(+), 6 deletions(-) Reviewed-by: Douglas Anderson <dianders@chromium.org>
Hi Doug, 在 2016年11月15日 02:15, Doug Anderson 写道: > William > > On Sun, Nov 13, 2016 at 11:01 PM, William Wu <wulf@rock-chips.com> wrote: >> Since we needs to delay ~1ms to wait for 480MHz output clock >> of USB2 PHY to become stable after turn on it, the delay time >> is pretty long for something that's supposed to be "atomic" >> like a clk_enable(). Consider that clk_enable() will disable >> interrupt and that a 1ms interrupt latency is not sensible. >> >> The 480MHz output clock should be handled in prepare callbacks >> which support gate a clk if the operation may sleep. >> >> Signed-off-by: William Wu <wulf@rock-chips.com> >> --- >> drivers/phy/phy-rockchip-inno-usb2.c | 12 ++++++------ >> 1 file changed, 6 insertions(+), 6 deletions(-) > Reviewed-by: Douglas Anderson <dianders@chromium.org> Thanks! I'll add Reviewed-by. > > >
diff --git a/drivers/phy/phy-rockchip-inno-usb2.c b/drivers/phy/phy-rockchip-inno-usb2.c index ac20310..365e077 100644 --- a/drivers/phy/phy-rockchip-inno-usb2.c +++ b/drivers/phy/phy-rockchip-inno-usb2.c @@ -153,7 +153,7 @@ static inline bool property_enabled(struct rockchip_usb2phy *rphy, return tmp == reg->enable; } -static int rockchip_usb2phy_clk480m_enable(struct clk_hw *hw) +static int rockchip_usb2phy_clk480m_prepare(struct clk_hw *hw) { struct rockchip_usb2phy *rphy = container_of(hw, struct rockchip_usb2phy, clk480m_hw); @@ -172,7 +172,7 @@ static int rockchip_usb2phy_clk480m_enable(struct clk_hw *hw) return 0; } -static void rockchip_usb2phy_clk480m_disable(struct clk_hw *hw) +static void rockchip_usb2phy_clk480m_unprepare(struct clk_hw *hw) { struct rockchip_usb2phy *rphy = container_of(hw, struct rockchip_usb2phy, clk480m_hw); @@ -181,7 +181,7 @@ static void rockchip_usb2phy_clk480m_disable(struct clk_hw *hw) property_enable(rphy, &rphy->phy_cfg->clkout_ctl, false); } -static int rockchip_usb2phy_clk480m_enabled(struct clk_hw *hw) +static int rockchip_usb2phy_clk480m_prepared(struct clk_hw *hw) { struct rockchip_usb2phy *rphy = container_of(hw, struct rockchip_usb2phy, clk480m_hw); @@ -197,9 +197,9 @@ rockchip_usb2phy_clk480m_recalc_rate(struct clk_hw *hw, } static const struct clk_ops rockchip_usb2phy_clkout_ops = { - .enable = rockchip_usb2phy_clk480m_enable, - .disable = rockchip_usb2phy_clk480m_disable, - .is_enabled = rockchip_usb2phy_clk480m_enabled, + .prepare = rockchip_usb2phy_clk480m_prepare, + .unprepare = rockchip_usb2phy_clk480m_unprepare, + .is_prepared = rockchip_usb2phy_clk480m_prepared, .recalc_rate = rockchip_usb2phy_clk480m_recalc_rate, };
Since we needs to delay ~1ms to wait for 480MHz output clock of USB2 PHY to become stable after turn on it, the delay time is pretty long for something that's supposed to be "atomic" like a clk_enable(). Consider that clk_enable() will disable interrupt and that a 1ms interrupt latency is not sensible. The 480MHz output clock should be handled in prepare callbacks which support gate a clk if the operation may sleep. Signed-off-by: William Wu <wulf@rock-chips.com> --- drivers/phy/phy-rockchip-inno-usb2.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-)