From patchwork Tue Nov 15 09:14:57 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Nowicki X-Patchwork-Id: 9429235 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id BD8B160484 for ; Tue, 15 Nov 2016 09:19:36 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 96F02287ED for ; Tue, 15 Nov 2016 09:19:36 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8BC09287F7; Tue, 15 Nov 2016 09:19:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED, T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 212BA287ED for ; Tue, 15 Nov 2016 09:19:36 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1c6ZsN-0002I5-Q5; Tue, 15 Nov 2016 09:17:59 +0000 Received: from mail-qt0-x231.google.com ([2607:f8b0:400d:c0d::231]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1c6Zrm-0001xN-Jq for linux-arm-kernel@lists.infradead.org; Tue, 15 Nov 2016 09:17:26 +0000 Received: by mail-qt0-x231.google.com with SMTP id c47so64517454qtc.2 for ; Tue, 15 Nov 2016 01:17:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=9ixGCf40ReYyt98uqq+UHNTMRQKkMlifGRgWMMtbDNU=; b=IiRuUdKlvr8zL9hwseuS9+Se3AdIIvHFR/J+p6D3DJsGTaE0c62Zca//WNXLJcB+Px 6ukWVztQwjnixdwdXzPsoCTV+4jOYkzyjzzONJUkXgzSLOnljCTrAlrWNizrBqfeYB31 78J1hOdLgpzhbgilRhNJkv9vadXisyrZGYxgjO4ltGsqKbFbGCOSjB35cn9OjfF0LmDD lTtcLOQfLuDQ1JD/3/eGXfXS39YMw8TxeQny9Edm8Q94XRm0DGPMatUhuSJN6Ms0ftvv drDWaAnbILGh2zO0eMTPDHmDP7dfwxOyPxAD+isNoWrgkPcNSjmH78iVprsTLvfNTVuO zbGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=9ixGCf40ReYyt98uqq+UHNTMRQKkMlifGRgWMMtbDNU=; b=L/g515EZ9Q7enNNe+SA40KDfBV08NLbS69Ir6CB2OlDx4/rvUV+q0JU+5Zf84kcspv 2X3h5RaH/68MMjIdGUdbQzWmTH9COPulFM39Ygglj1pms3eO/XxkGNuhpvMiCHAlNPhw dVRuDhnBuGhTVZMN9PER1glDsfQmbxtdxufOfw1ecMCIDFGGRl4APCERhlGSrdlCfNFp EvmcPGzGjHLrnzzfoODdlCNao9KGwYoB1nr0sDZrna2Z735ip6reUyghAEgSXKo7JJ0c 3Dg+0CwO0MSYn1nicfVtg0gOBCdaztt0C4NGktYWe7tgW7B8Q/G+5vhFnyLRr6rTceMp Qr6A== X-Gm-Message-State: ABUngvf9ny4nzmKg8jteu6K3McaZoThUKJyahdmsC9tEmn2fweLdmp5oDfbm8N2750uNKw== X-Received: by 10.25.208.14 with SMTP id h14mr10100213lfg.73.1479201420888; Tue, 15 Nov 2016 01:17:00 -0800 (PST) Received: from tn-desktop.semihalf.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id 31sm6128287lfv.21.2016.11.15.01.16.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 15 Nov 2016 01:17:00 -0800 (PST) From: Tomasz Nowicki To: helgaas@kernel.org, will.deacon@arm.com, catalin.marinas@arm.com, rafael@kernel.org, Lorenzo.Pieralisi@arm.com Subject: [PATCH V1 1/2] PCI: thunder: Enable ACPI PCI controller for ThunderX pass2.x silicon version Date: Tue, 15 Nov 2016 10:14:57 +0100 Message-Id: <1479201298-25494-2-git-send-email-tn@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1479201298-25494-1-git-send-email-tn@semihalf.com> References: <1479201298-25494-1-git-send-email-tn@semihalf.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20161115_011723_104195_85BE8453 X-CRM114-Status: GOOD ( 18.99 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jchandra@broadcom.com, gabriele.paoloni@huawei.com, arnd@arndb.de, ard.biesheuvel@linaro.org, linux-pci@vger.kernel.org, linaro-acpi@lists.linaro.org, ddaney@caviumnetworks.com, jeremy.linton@arm.com, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, robert.richter@caviumnetworks.com, msalter@redhat.com, liudongdong3@huawei.com, jcm@redhat.com, Tomasz Nowicki , mw@semihalf.com, andrea.gallo@linaro.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP ThunderX PCIe controller to off-chip devices (so-called PEM) is not fully compliant with ECAM standard. It uses non-standard configuration space accessors (see pci_thunder_pem_ops) and custom configuration space granulation (see bus_shift = 24). In order to access configuration space and probe PEM as ACPI based PCI host controller we need to add MCFG quirk infrastructure. This involves: 1. thunder_pem_init() ACPI extension so that we can probe PEM-specific register ranges analogously to DT 2. Export PEM pci_thunder_pem_ops structure so it is visible to MCFG quirk code. 3. New quirk entries for each PEM segment. Each contains platform IDs, mentioned pci_thunder_pem_ops and CFG resources. Quirk is considered for ThunderX silicon pass2.x only which is identified via MCFG revision 1. Signed-off-by: Tomasz Nowicki --- drivers/acpi/pci_mcfg.c | 20 +++++++ drivers/pci/host/pci-thunder-pem.c | 107 ++++++++++++++++++++++++++++++++----- include/linux/pci-ecam.h | 4 ++ 3 files changed, 117 insertions(+), 14 deletions(-) diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c index ac21db3..e4e2b9b 100644 --- a/drivers/acpi/pci_mcfg.c +++ b/drivers/acpi/pci_mcfg.c @@ -57,6 +57,26 @@ static struct mcfg_fixup mcfg_quirks[] = { { "QCOM ", "QDF2432 ", 1, 5, MCFG_BUS_ANY, &pci_32b_ops }, { "QCOM ", "QDF2432 ", 1, 6, MCFG_BUS_ANY, &pci_32b_ops }, { "QCOM ", "QDF2432 ", 1, 7, MCFG_BUS_ANY, &pci_32b_ops }, +#ifdef CONFIG_PCI_HOST_THUNDER_PEM +#define THUNDER_MCFG_RES(addr, node) \ + DEFINE_RES_MEM(addr + (node << 44), 0x39 * SZ_16M) +#define THUNDER_MCFG_QUIRK(rev, node) \ + { "CAVIUM", "THUNDERX", rev, 4 + (10 * node), MCFG_BUS_ANY, \ + &pci_thunder_pem_ops, THUNDER_MCFG_RES(0x88001f000000UL, node) }, \ + { "CAVIUM", "THUNDERX", rev, 5 + (10 * node), MCFG_BUS_ANY, \ + &pci_thunder_pem_ops, THUNDER_MCFG_RES(0x884057000000UL, node) }, \ + { "CAVIUM", "THUNDERX", rev, 6 + (10 * node), MCFG_BUS_ANY, \ + &pci_thunder_pem_ops, THUNDER_MCFG_RES(0x88808f000000UL, node) }, \ + { "CAVIUM", "THUNDERX", rev, 7 + (10 * node), MCFG_BUS_ANY, \ + &pci_thunder_pem_ops, THUNDER_MCFG_RES(0x89001f000000UL, node) }, \ + { "CAVIUM", "THUNDERX", rev, 8 + (10 * node), MCFG_BUS_ANY, \ + &pci_thunder_pem_ops, THUNDER_MCFG_RES(0x894057000000UL, node) }, \ + { "CAVIUM", "THUNDERX", rev, 9 + (10 * node), MCFG_BUS_ANY, \ + &pci_thunder_pem_ops, THUNDER_MCFG_RES(0x89808f000000UL, node) } + /* SoC pass2.x */ + THUNDER_MCFG_QUIRK(1, 0UL), + THUNDER_MCFG_QUIRK(1, 1UL), +#endif }; static char mcfg_oem_id[ACPI_OEM_ID_SIZE]; diff --git a/drivers/pci/host/pci-thunder-pem.c b/drivers/pci/host/pci-thunder-pem.c index 6abaf80..7bdc4cd 100644 --- a/drivers/pci/host/pci-thunder-pem.c +++ b/drivers/pci/host/pci-thunder-pem.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include @@ -284,6 +285,84 @@ static int thunder_pem_config_write(struct pci_bus *bus, unsigned int devfn, return pci_generic_config_write(bus, devfn, where, size, val); } +#ifdef CONFIG_ACPI + +/* + * Retrieve PEM bridge register base and size from PNP0C02 sub-device under + * the RC. + * + * Device (RES0) + * { + * Name (_HID, "THRX0002") + * Name (_CID, "PNP0C02") + * Name (_CRS, ResourceTemplate () { + * // Device specific registers range + * QWordMemory(ResourceConsumer, PosDecode, MinFixed, + * MaxFixed, Cacheable, ReadWrite, 0, + * 0x87e0c2000000, 0x87E0C2FFFFFF, 0, 0x1000000) + * }) + * } + */ + +static const struct acpi_device_id thunder_pem_reg_ids[] = { + {"THRX0002", 0}, + {"", 0}, +}; + +static struct resource *thunder_pem_acpi_res(struct pci_config_window *cfg) +{ + struct device *dev = cfg->parent; + struct acpi_device *adev = to_acpi_device(dev); + struct acpi_device *child_adev; + struct resource *res_pem; + + res_pem = devm_kzalloc(dev, sizeof(*res_pem), GFP_KERNEL); + if (!res_pem) { + dev_err(dev, "failed to allocate PEM resource\n"); + return NULL; + } + + list_for_each_entry(child_adev, &adev->children, node) { + struct resource_entry *entry; + struct list_head list; + unsigned long flags; + int ret; + + ret = acpi_match_device_ids(child_adev, thunder_pem_reg_ids); + if (ret) + continue; + + INIT_LIST_HEAD(&list); + flags = IORESOURCE_MEM; + ret = acpi_dev_get_resources(child_adev, &list, + acpi_dev_filter_resource_type_cb, + (void *)flags); + if (ret < 0) { + dev_err(&child_adev->dev, + "failed to parse _CRS method, error code %d\n", + ret); + return NULL; + } else if (ret == 0) { + dev_err(&child_adev->dev, + "no memory resources present in _CRS\n"); + return NULL; + } + + entry = list_first_entry(&list, struct resource_entry, node); + *res_pem = *entry->res; + acpi_dev_free_resource_list(&list); + return res_pem; + } + + return NULL; +} +#else +static struct resource *thunder_pem_acpi_res(struct pci_config_window *cfg) +{ + return NULL; +} +#endif + static int thunder_pem_init(struct pci_config_window *cfg) { struct device *dev = cfg->parent; @@ -292,24 +371,24 @@ static int thunder_pem_init(struct pci_config_window *cfg) struct thunder_pem_pci *pem_pci; struct platform_device *pdev; - /* Only OF support for now */ - if (!dev->of_node) - return -EINVAL; - pem_pci = devm_kzalloc(dev, sizeof(*pem_pci), GFP_KERNEL); if (!pem_pci) return -ENOMEM; - pdev = to_platform_device(dev); - - /* - * The second register range is the PEM bridge to the PCIe - * bus. It has a different config access method than those - * devices behind the bridge. - */ - res_pem = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (acpi_disabled) { + pdev = to_platform_device(dev); + + /* + * The second register range is the PEM bridge to the PCIe + * bus. It has a different config access method than those + * devices behind the bridge. + */ + res_pem = platform_get_resource(pdev, IORESOURCE_MEM, 1); + } else { + res_pem = thunder_pem_acpi_res(cfg); + } if (!res_pem) { - dev_err(dev, "missing \"reg[1]\"property\n"); + dev_err(dev, "missing configuration region\n"); return -EINVAL; } @@ -332,7 +411,7 @@ static int thunder_pem_init(struct pci_config_window *cfg) return 0; } -static struct pci_ecam_ops pci_thunder_pem_ops = { +struct pci_ecam_ops pci_thunder_pem_ops = { .bus_shift = 24, .init = thunder_pem_init, .pci_ops = { diff --git a/include/linux/pci-ecam.h b/include/linux/pci-ecam.h index f5740b7..3f2a98f 100644 --- a/include/linux/pci-ecam.h +++ b/include/linux/pci-ecam.h @@ -58,6 +58,10 @@ void __iomem *pci_ecam_map_bus(struct pci_bus *bus, unsigned int devfn, int where); /* default ECAM ops */ extern struct pci_ecam_ops pci_generic_ecam_ops; +/* ECAM ops for known quirks */ +#ifdef CONFIG_PCI_HOST_THUNDER_PEM +extern struct pci_ecam_ops pci_thunder_pem_ops; +#endif /* ops for buggy ECAM that supports only 32-bit accesses */ extern struct pci_ecam_ops pci_32b_ops;