From patchwork Fri Nov 25 04:35:51 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 9446459 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id E6D526071C for ; Fri, 25 Nov 2016 04:39:13 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D329527F9A for ; Fri, 25 Nov 2016 04:39:13 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C465B27FA3; Fri, 25 Nov 2016 04:39:13 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED, T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 8EA4927F9A for ; Fri, 25 Nov 2016 04:39:09 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1cA8Fo-0000Ll-RV; Fri, 25 Nov 2016 04:36:52 +0000 Received: from mail-qt0-x22d.google.com ([2607:f8b0:400d:c0d::22d]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1cA8Fe-0000ID-CL for linux-arm-kernel@lists.infradead.org; Fri, 25 Nov 2016 04:36:46 +0000 Received: by mail-qt0-x22d.google.com with SMTP id c47so56175912qtc.2 for ; Thu, 24 Nov 2016 20:36:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=tyrHJ2lqg7q88cTCBmnKVuESLz74fFUcDwLCB2zuCys=; b=YmhPoopeq1ko1IRo2S/aCQeT5OHTskCN7yJ0dnVaUNRzPXUMAZZnMGX+PnnvXUDObn qH2+Ovi+uIpj+tL3JWXEa2rq6/WsicZnaFVAKdFXRxmD2CvUJQqqR3qUoCuo262QOdpW 7AHuvItBADXffOAirMUHuN7rPor5Bs6y4qhK0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=tyrHJ2lqg7q88cTCBmnKVuESLz74fFUcDwLCB2zuCys=; b=k8VVHaKuyZYmLr/BMHwr6iAXnCPvKGG+chA7N73moMsUKACXnFQhOiuo2GQM/BKW9j /o2D/hLgki8YFd1tJr6lyVTJE4Rs4I54jXwsKp1Yl73uFO0yNzww6eS5a4ciYyelPFCP 4XachmHHWouCSH2OJ5wUcDUTRcXnsD9l4GkuyHIf+oSgGDJy7MWHKd9r0kCcP+bqBNnB AMFnUm/LNQp+MQFSWydLRT/wD0E8IQ4ZO426F27Zo+BwgF84SQtBlBSkcRrFRe6sW5ph yvsByLN5lzvlfGc0UnMikMXwows4NDYyAl9+lUSV2F7u3SEiWdsNvm2PU4e1O+5m2o5x gZhQ== X-Gm-Message-State: AKaTC01lb+ZscXdILvxx/Pz5Uh86zWamfu46vehbx949WTb0+iud0XmruGqLuxR7Rfv8ey2u X-Received: by 10.237.33.156 with SMTP id l28mr5542800qtc.111.1480048580748; Thu, 24 Nov 2016 20:36:20 -0800 (PST) Received: from anup-HP-Compaq-8100-Elite-CMT-PC.dhcp.avagotech.net ([192.19.237.250]) by smtp.gmail.com with ESMTPSA id s41sm20519042qtc.39.2016.11.24.20.36.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 24 Nov 2016 20:36:20 -0800 (PST) From: Anup Patel To: Jassi Brar , Rob Herring Subject: [PATCH 2/2] dt-bindings: Add DT bindings info for FlexRM mailbox driver Date: Fri, 25 Nov 2016 10:05:51 +0530 Message-Id: <1480048551-3285-3-git-send-email-anup.patel@broadcom.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1480048551-3285-1-git-send-email-anup.patel@broadcom.com> References: <1480048551-3285-1-git-send-email-anup.patel@broadcom.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20161124_203642_650333_7B3307AF X-CRM114-Status: GOOD ( 16.28 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Anup Patel , Scott Branden , Ray Jui , linux-kernel@vger.kernel.org, Pramod KUMAR , bcm-kernel-feedback-list@broadcom.com, Rob Rice , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds device tree bindings document for the FlexRM mailbox driver. Reviewed-by: Ray Jui Reviewed-by: Scott Branden Signed-off-by: Anup Patel --- .../bindings/mailbox/brcm,flexrm-mbox.txt | 60 ++++++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/brcm,flexrm-mbox.txt diff --git a/Documentation/devicetree/bindings/mailbox/brcm,flexrm-mbox.txt b/Documentation/devicetree/bindings/mailbox/brcm,flexrm-mbox.txt new file mode 100644 index 0000000..7969b1c --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/brcm,flexrm-mbox.txt @@ -0,0 +1,60 @@ +Broadcom FlexRM Mailbox Driver +=============================== +The Broadcom FlexRM ring manager provides a set of rings which can be +used to submit work to offload engines. An SoC may have multiple FlexRM +hardware blocks. There is one device tree entry per block. The FlexRM +mailbox drivers creates a mailbox instance using FlexRM rings where +each mailbox channel is a separate FlexRM ring. + +Required properties: +-------------------- +- compatible: Should be "brcm,flexrm-mbox" +- reg: Specifies base physical address and size of the FlexRM + ring registers +- msi-parent: Phandles (and potential Device IDs) to MSI controllers + The FlexRM engine will send MSIs (instead of wired + interrupts) to CPU. There is one MSI for each FlexRM ring. + Refer devicetree/bindings/interrupt-controller/msi.txt +- #mbox-cells: Specifies the number of cells needed to encode a mailbox + channel. This should be 3. + + The 1st cell is the mailbox channel number. + + The 2nd cell contains MSI completion threshold. This is the + number of completion messages for which FlexRM will inject + one MSI interrupt to CPU. + + The 3nd cell contains MSI timer value representing time for + which FlexRM will wait to accumulate N completion messages + where N is the value specified by 2nd cell above. If FlexRM + does not get required number of completion messages in time + specified by this cell then it will inject one MSI interrupt + to CPU provided atleast one completion message is available. + +Optional properties: +-------------------- +- dma-coherent: Present if DMA operations made by the FlexRM engine (such + as DMA descriptor access, access to buffers pointed by DMA + descriptors and read/write pointer updates to DDR) are + cache coherent with the CPU. + +Example: +-------- +crypto_mbox: mbox@67000000 { + compatible = "brcm,flexrm-mbox"; + reg = <0x67000000 0x200000>; + msi-parent = <&gic_its 0x7f00>; + #mbox-cells = <3>; +}; + +crypto_client { + ... + mboxes = <&crypto_mbox 0 0x1 0xffff>, + <&crypto_mbox 1 0x1 0xffff>, + <&crypto_mbox 16 0x1 0xffff>, + <&crypto_mbox 17 0x1 0xffff>, + <&crypto_mbox 30 0x1 0xffff>, + <&crypto_mbox 31 0x1 0xffff>; + }; + ... +};