From patchwork Sat Nov 26 08:00:47 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ding Tianhong X-Patchwork-Id: 9448315 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 4E04E60487 for ; Sat, 26 Nov 2016 08:06:46 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3B2141FF21 for ; Sat, 26 Nov 2016 08:06:46 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2D13E26BE9; Sat, 26 Nov 2016 08:06:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id BDD4E1FF21 for ; Sat, 26 Nov 2016 08:06:45 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1cAXzB-0007XE-CR; Sat, 26 Nov 2016 08:05:25 +0000 Received: from szxga02-in.huawei.com ([119.145.14.65]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1cAXy2-0005EZ-8F for linux-arm-kernel@lists.infradead.org; Sat, 26 Nov 2016 08:04:22 +0000 Received: from 172.24.1.47 (EHLO SZXEML423-HUB.china.huawei.com) ([172.24.1.47]) by szxrg02-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id DRH44415; Sat, 26 Nov 2016 16:01:17 +0800 (CST) Received: from localhost (10.177.23.32) by SZXEML423-HUB.china.huawei.com (10.82.67.154) with Microsoft SMTP Server id 14.3.235.1; Sat, 26 Nov 2016 16:01:09 +0800 From: Ding Tianhong To: , , , , , , , , , , Subject: [PATCH v4 5/6] arm64: arch_timer: apci: Introduce a generic aquirk framework for erratum Date: Sat, 26 Nov 2016 16:00:47 +0800 Message-ID: <1480147248-12828-6-git-send-email-dingtianhong@huawei.com> X-Mailer: git-send-email 1.8.5.2.msysgit.0 In-Reply-To: <1480147248-12828-1-git-send-email-dingtianhong@huawei.com> References: <1480147248-12828-1-git-send-email-dingtianhong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.23.32] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20161126_000415_655657_5EA2084B X-CRM114-Status: GOOD ( 11.15 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ding Tianhong Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Hanjun Guo Introduce a general quirk framework for each timer erratum in ACPI, which use the oem information in GTDT table for platform specific erratums. The struct gtdt_arch_timer_fixup is introduced to record the oem information to match the quirk and handle the erratum. v3: Introduce a generic aquick framework for erratum in ACPI mode. v4: rename the quirk handler parameter to make it more generic, and avoid break loop when handling the quirk becasue it need to support multi quirks handler. Signed-off-by: Hanjun Guo Signed-off-by: Ding Tianhong --- drivers/clocksource/arm_arch_timer.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index 3d59af1..d4f4a0d 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -1068,6 +1068,39 @@ static int __init arch_timer_mem_init(struct device_node *np) arch_timer_mem_init); #ifdef CONFIG_ACPI +struct gtdt_arch_timer_fixup { + char oem_id[ACPI_OEM_ID_SIZE]; + char oem_table_id[ACPI_OEM_TABLE_ID_SIZE]; + u32 oem_revision; + + /* quirk handler for arch timer erratum */ + void (*handler)(void *context); + void *context; +}; + +/* note: this needs to be updated according to the doc of OEM ID + * and TABLE ID for different board. + */ +struct gtdt_arch_timer_fixup arch_timer_quirks[] __initdata = { +}; + +void __init arch_timer_acpi_quirks_handler(char *oem_id, + char *oem_table_id, + u32 oem_revision) +{ + struct gtdt_arch_timer_fixup *quirks = arch_timer_quirks; + int i; + + for (i = 0; i < ARRAY_SIZE(arch_timer_quirks); i++, quirks++) { + if (!memcmp(quirks->oem_id, oem_id, ACPI_OEM_ID_SIZE) && + !memcmp(quirks->oem_table_id, oem_table_id, ACPI_OEM_TABLE_ID_SIZE) && + quirks->oem_revision == oem_revision) { + if (quirks->handler && quirks->context) + quirks->handler(quirks->context); + } + } +} + static int __init map_generic_timer_interrupt(u32 interrupt, u32 flags) { int trigger, polarity; @@ -1094,6 +1127,9 @@ static int __init arch_timer_acpi_init(struct acpi_table_header *table) return -EINVAL; } + arch_timer_acpi_quirks_handler(table->oem_id, table->oem_table_id, + table->oem_revision); + gtdt = container_of(table, struct acpi_table_gtdt, header); arch_timers_present |= ARCH_CP15_TIMER;