From patchwork Fri Dec 2 02:27:32 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brian Norris X-Patchwork-Id: 9457697 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id DD2646074E for ; Fri, 2 Dec 2016 02:36:48 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CED9927F80 for ; Fri, 2 Dec 2016 02:36:48 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C3C46284F1; Fri, 2 Dec 2016 02:36:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED, T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 5D18627F80 for ; Fri, 2 Dec 2016 02:36:48 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1cCdgp-0004SZ-4o; Fri, 02 Dec 2016 02:35:07 +0000 Received: from mail-pg0-x232.google.com ([2607:f8b0:400e:c05::232]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1cCdfl-0003tM-Jq for linux-arm-kernel@lists.infradead.org; Fri, 02 Dec 2016 02:34:07 +0000 Received: by mail-pg0-x232.google.com with SMTP id f188so101364560pgc.3 for ; Thu, 01 Dec 2016 18:33:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=8APMFWojYXrtfqPymOqPqB/i8QTThquMu/v/SY4Omfw=; b=baoMn9Bhdp1uC/GGvTGXOWRtkYuf3NJLPOjaZJ+YO6f1+f+/457GBbX1QuqqG/WNZc vH5jbmA5HnSQfrd3YEAEzgSJF/5PNuLEK0UdYCGUljGZIw7/tJwhNX+Xv6MePWOTXlrc fMkotSdbmKt9rCsRWPYD24X/bIKl0ZdCq872I= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8APMFWojYXrtfqPymOqPqB/i8QTThquMu/v/SY4Omfw=; b=V/b+NFzx8jO/CyaDzw+VFpwm74657LhxzZ5iGfxH77awtkdp9213X5iK2kbFKB9fhb U9drvaNPpEMw+DU5KGcJ1vq0Tkqdzd1tv/L5e1Uttgy1BHpcx6blmoUk1F+qO0wPrutN MdaRkVDsub0Ogf8kQQSOvFqhyesfmzUlEjVqZqlZyBNwx6NEi7sJM4HJQD8aE0qeuo34 dwtec633yPG5/efO/DzeVaQ2hh9WAPO8YqlN5teaO6IpFqrk3djpPmP2lAgQMpHUd3zR Mb3lUcMBe0xXJljMbLtYEOVSBvk+/mrL2vXi3J0rHJ0A6s8aKN/6bc9v62xDVmv1Bk3d oiAA== X-Gm-Message-State: AKaTC02is7LoqoVZEs7I1EUhCxOpOCL8hKxxtR3T0s9JP1uEVUrCVwpCRylysLOr8gIv20w6 X-Received: by 10.84.215.138 with SMTP id l10mr91122338pli.166.1480646024012; Thu, 01 Dec 2016 18:33:44 -0800 (PST) Received: from ban.mtv.corp.google.com ([172.22.64.120]) by smtp.gmail.com with ESMTPSA id 16sm3090085pfy.4.2016.12.01.18.33.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 01 Dec 2016 18:33:43 -0800 (PST) From: Brian Norris To: Heiko Stuebner Subject: [PATCH 8/9] arm64: dts: rockchip: partially describe PWM regulators for Gru Date: Thu, 1 Dec 2016 18:27:32 -0800 Message-Id: <1480645653-36943-9-git-send-email-briannorris@chromium.org> X-Mailer: git-send-email 2.8.0.rc3.226.g39d4020 In-Reply-To: <1480645653-36943-1-git-send-email-briannorris@chromium.org> References: <1480645653-36943-1-git-send-email-briannorris@chromium.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20161201_183401_811258_7DB5441F X-CRM114-Status: GOOD ( 13.61 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Brian Norris , Doug Anderson , linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, Rob Herring , Chris Zhong , Stephen Barber , linux-arm-kernel@lists.infradead.org, Caesar Wang MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP We need to add regulators to the CPU nodes, so cpufreq doesn't think it can crank up the clock speed without changing the voltage. However, we don't yet have the DT bindings to fully describe the Over Voltage Protection (OVP) circuits on these boards. Without that description, we might end up changing the voltage too much, too fast. Add the pwm-regulator descriptions and associate the CPU OPPs, but leave them disabled. Signed-off-by: Brian Norris --- arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 146 +++++++++++++++++++++++++++ 1 file changed, 146 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi index 59b452504106..90adfb5cba38 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi @@ -172,6 +172,98 @@ vin-supply = <&ppvar_sys>; }; + ppvar_bigcpu: ppvar-bigcpu { + compatible = "pwm-regulator"; + regulator-name = "ppvar_bigcpu"; + /* + * OVP circuit requires special handling which is not yet + * represented. Keep disabled for now. + */ + status = "disabled"; + + pwms = <&pwm1 0 3337 0>; + + /* EC turns on w/ ap_core_en; always on for AP */ + regulator-always-on; + regulator-boot-on; + + regulator-min-microvolt = <798674>; + regulator-max-microvolt = <1302172>; + + pwm-supply = <&ppvar_sys>; + pwm-dutycycle-range = <100 0>; + pwm-dutycycle-unit = <100>; + }; + + ppvar_litcpu: ppvar-litcpu { + compatible = "pwm-regulator"; + regulator-name = "ppvar_litcpu"; + /* + * OVP circuit requires special handling which is not yet + * represented. Keep disabled for now. + */ + status = "disabled"; + + pwms = <&pwm2 0 3337 0>; + + /* EC turns on w/ ap_core_en; always on for AP */ + regulator-always-on; + regulator-boot-on; + + regulator-min-microvolt = <799065>; + regulator-max-microvolt = <1303738>; + + pwm-supply = <&ppvar_sys>; + pwm-dutycycle-range = <100 0>; + pwm-dutycycle-unit = <100>; + }; + + ppvar_gpu: ppvar-gpu { + compatible = "pwm-regulator"; + regulator-name = "ppvar_gpu"; + /* + * OVP circuit requires special handling which is not yet + * represented. Keep disabled for now. + */ + status = "disabled"; + + pwms = <&pwm0 0 3337 0>; + + /* EC turns on w/ ap_core_en; always on for AP */ + regulator-always-on; + regulator-boot-on; + + regulator-min-microvolt = <785782>; + regulator-max-microvolt = <1217729>; + + pwm-supply = <&ppvar_sys>; + pwm-dutycycle-range = <100 0>; + pwm-dutycycle-unit = <100>; + }; + + ppvar_centerlogic: ppvar-centerlogic { + compatible = "pwm-regulator"; + regulator-name = "ppvar_centerlogic"; + /* + * OVP circuit requires special handling which is not yet + * represented. Keep disabled for now. + */ + status = "disabled"; + + pwms = <&pwm3 0 3337 0>; + + /* EC turns on w/ ppvar_centerlogic_en; always on for AP */ + regulator-always-on; + regulator-boot-on; + + regulator-min-microvolt = <800069>; + regulator-max-microvolt = <1049692>; + + pwm-supply = <&ppvar_sys>; + pwm-dutycycle-range = <100 0>; + pwm-dutycycle-unit = <100>; + }; + /* Schematics call this PPVAR even though it's fixed */ ppvar_logic: ppvar-logic { compatible = "regulator-fixed"; @@ -444,6 +536,60 @@ }; }; +/* + * Set some suspend operating points to avoid OVP in suspend + * + * When we go into S3 ARM Trusted Firmware will transition our PWM regulators + * from wherever they're at back to the "default" operating point (whatever + * voltage we get when we set the PWM pins to "input"). + * + * This quick transition under light load has the possibility to trigger the + * regulator "over voltage protection" (OVP). + * + * To make extra certain that we don't hit this OVP at suspend time, we'll + * transition to a voltage that's much closer to the default (~1.0 V) so that + * there will not be a big jump. Technically we only need to get within 200 mV + * of the default voltage, but the speed here should be fast enough and we need + * suspend/resume to be rock solid. + */ + +&cluster0_opp { + opp05 { + opp-suspend; + }; +}; + +&cluster1_opp { + opp06 { + opp-suspend; + }; +}; + +&cpu_l0 { + cpu-supply = <&ppvar_litcpu>; +}; + +&cpu_l1 { + cpu-supply = <&ppvar_litcpu>; +}; + +&cpu_l2 { + cpu-supply = <&ppvar_litcpu>; +}; + +&cpu_l3 { + cpu-supply = <&ppvar_litcpu>; +}; + +&cpu_b0 { + cpu-supply = <&ppvar_bigcpu>; +}; + +&cpu_b1 { + cpu-supply = <&ppvar_bigcpu>; +}; + + &cru { assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,