From patchwork Fri Dec 2 18:55:59 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 9458971 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id CF66360236 for ; Fri, 2 Dec 2016 19:00:05 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BF03C28584 for ; Fri, 2 Dec 2016 19:00:05 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id AFB0928590; Fri, 2 Dec 2016 19:00:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 95C8328584 for ; Fri, 2 Dec 2016 19:00:04 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1cCt2S-0003gn-QV; Fri, 02 Dec 2016 18:58:28 +0000 Received: from foss.arm.com ([217.140.101.70]) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1cCt0n-0002YL-D5 for linux-arm-kernel@lists.infradead.org; Fri, 02 Dec 2016 18:56:47 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C6C0615B2; Fri, 2 Dec 2016 10:56:04 -0800 (PST) Received: from beelzebub.ast.arm.com (unknown [10.118.96.220]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 581513F318; Fri, 2 Dec 2016 10:56:04 -0800 (PST) From: Jeremy Linton To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v11 5/7] arm64: pmu: Detect multiple generic PMUs and append counter Date: Fri, 2 Dec 2016 12:55:59 -0600 Message-Id: <1480704961-6910-6-git-send-email-jeremy.linton@arm.com> X-Mailer: git-send-email 2.5.5 In-Reply-To: <1480704961-6910-1-git-send-email-jeremy.linton@arm.com> References: <1480704961-6910-1-git-send-email-jeremy.linton@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20161202_105645_745467_8C1B0633 X-CRM114-Status: GOOD ( 14.27 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, steve.capper@arm.com, mlangsdorf@redhat.com, punit.agrawal@arm.com, will.deacon@arm.com, linux@armlinux.org.uk, linux-acpi@vger.kernel.org, msalter@redhat.com MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP In heterogeneous CPU systems its likely that there are multiple PMU types. If a system is using the generic armv8_pmuv3 rather than a PMU with a hard-coded set of events then we want to uniquely identify each PMU in /sys. We do this by appending an "_x" to the pmu name. This then creates PMUs like, "armv8_pmuv3" and "armv8_pmuv3_1", "armv8_pmuv3_2" for a system with 3 PMU types. Signed-off-by: Jeremy Linton --- arch/arm64/kernel/perf_event.c | 2 +- drivers/perf/arm_pmu.c | 20 ++++++++++++++++++++ include/linux/perf/arm_pmu.h | 1 + 3 files changed, 22 insertions(+), 1 deletion(-) diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index 57ae9d9..0fbd7ef 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -1002,7 +1002,7 @@ static void armv8_pmu_init(struct arm_pmu *cpu_pmu) static int armv8_pmuv3_init(struct arm_pmu *cpu_pmu) { armv8_pmu_init(cpu_pmu); - cpu_pmu->name = "armv8_pmuv3"; + cpu_pmu->name = ARMV8_PMUV3_DESCRIPTION; cpu_pmu->map_event = armv8_pmuv3_map_event; cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = &armv8_pmuv3_events_attr_group; diff --git a/drivers/perf/arm_pmu.c b/drivers/perf/arm_pmu.c index 00e98c5..f676573 100644 --- a/drivers/perf/arm_pmu.c +++ b/drivers/perf/arm_pmu.c @@ -1035,6 +1035,7 @@ int arm_pmu_device_probe(struct platform_device *pdev, const struct of_device_id *of_table, const struct pmu_probe_info *probe_table) { + static int duplicate_pmus; const struct of_device_id *of_id; const int (*init_fn)(struct arm_pmu *); struct device_node *node = pdev->dev.of_node; @@ -1075,6 +1076,25 @@ int arm_pmu_device_probe(struct platform_device *pdev, goto out_free; } + /* + * if this pmu declaration is a generic pmu and we have + * previously found a generic pmu on this platform + * then append a PMU number to the pmu name. This avoids + * changing the names of PMUs that are specific to a class + * of CPUs. The assumption is that if we match a specific PMU + * then it's unique, and another PMU in the system will match + * a different entry rather than needing the _number to + * assure its unique. + */ + if (!strcmp(pmu->name, ARMV8_PMUV3_DESCRIPTION)) { + if (duplicate_pmus) { + pmu->name = kasprintf(GFP_KERNEL, "%s_%d", + pmu->name, duplicate_pmus); + if (!pmu->name) + goto out_free; + } + duplicate_pmus++; + } ret = cpu_pmu_init(pmu); if (ret) diff --git a/include/linux/perf/arm_pmu.h b/include/linux/perf/arm_pmu.h index df1ba55..42b5edb 100644 --- a/include/linux/perf/arm_pmu.h +++ b/include/linux/perf/arm_pmu.h @@ -161,6 +161,7 @@ int arm_pmu_device_probe(struct platform_device *pdev, const struct pmu_probe_info *probe_table); #define ARMV8_PMU_PDEV_NAME "armv8-pmu" +#define ARMV8_PMUV3_DESCRIPTION "armv8_pmuv3" #endif /* CONFIG_ARM_PMU */