From patchwork Wed Dec 7 16:58:33 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anurup M X-Patchwork-Id: 9464901 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 67F4760459 for ; Wed, 7 Dec 2016 17:07:56 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5214D28435 for ; Wed, 7 Dec 2016 17:07:56 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 46FD6284F9; Wed, 7 Dec 2016 17:07:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED,FREEMAIL_FROM,RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 3624128442 for ; Wed, 7 Dec 2016 17:07:55 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1cEffQ-0007uB-SF; Wed, 07 Dec 2016 17:06:04 +0000 Received: from mail-pg0-x242.google.com ([2607:f8b0:400e:c05::242]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1cEfYf-00085v-6J for linux-arm-kernel@lists.infradead.org; Wed, 07 Dec 2016 17:00:05 +0000 Received: by mail-pg0-x242.google.com with SMTP id e9so23965638pgc.1 for ; Wed, 07 Dec 2016 08:58:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=tZZ4a18AQpxOxxQWyeicDcOHGlGT7qdqjRMV9yx390k=; b=EPvvlJhI1manOU3PEsJBlc1/sMLyaHFNgZrRuwqsSOqzkS/onG/5mhg/4nJXiNe9Cf TP6BBBkBtus/N9IgUfsewTQqBBsQKUJDrAbMoZS3bL/3yr73I6neadnTy+gjGBUc3MVw l7MT76Uh0rxfUc67RsjfqiRxysvdFefvgHRMZ4acPrAnYr9xVnp3EHHyyahiEiMTkddG iNF/HaRZht3NG7TW0QudMNq8+9z5wgDX8QSTnOmLm650etETaW+FexLA1dR0ReiLduTy vGbVWiygeM55ZK8Mv3C+qP+tS8f8a50ffpLkHe2gSM9RrbUyuPIOgRvoyCc1nephWGSk PPiA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=tZZ4a18AQpxOxxQWyeicDcOHGlGT7qdqjRMV9yx390k=; b=hkdxZu6StnkdLPeLmCxgP8V7ENGFF3eGmc2HkIlVjjhUck7mAHDFxa2kN9WtiWiH+t 0e6f4L73lblsGZ8gjPTmLom4R0HS8zP3eszzr3n3DchzrK1Tm11r1iH71QXMM9X/8ch0 FGTdN7VM9C9dn98tVAHfaCmUZ9eIdoZho+AKzxxBb+dKikGzGyYsAnLU/vnLfjC3pVus lHHCYxv5isztKXeLFY7qOJF1nCXywPhVSmg6U8rLqr/+PYVx2SBo5JW7TPIE7x9aAams eDYYH5b8L6X66qHXb7x6OqayjTTqBgmDhhEad4wUqt6IcrPD7FGI08w46VKJvdfbKyJp JZRA== X-Gm-Message-State: AKaTC02H8kHrF0z87sb9uoi9ioHdzt9itHfT9rWbVssh9Z7568WGm4dLttnrk0Fhqv0cKQ== X-Received: by 10.98.96.135 with SMTP id u129mr68981700pfb.141.1481129923554; Wed, 07 Dec 2016 08:58:43 -0800 (PST) Received: from localhost.localdomain ([14.141.5.98]) by smtp.gmail.com with ESMTPSA id 13sm43980181pfz.30.2016.12.07.08.58.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 07 Dec 2016 08:58:43 -0800 (PST) From: Anurup M X-Google-Original-From: Anurup M To: mark.rutland@arm.com, will.deacon@arm.com, robh+dt@kernel.org, xuwei5@hisilicon.com, catalin.marinas@arm.com Subject: [PATCH v2 10/10] dts: arm64: hip06: Add Hisilicon SoC PMU support Date: Wed, 7 Dec 2016 11:58:33 -0500 Message-Id: <1481129913-159858-1-git-send-email-anurup.m@huawei.com> X-Mailer: git-send-email 2.1.4 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20161207_085906_132319_4089968E X-CRM114-Status: UNSURE ( 9.58 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, anurupvasu@gmail.com, gabriele.paoloni@huawei.com, john.garry@huawei.com, shyju.pv@huawei.com, linux-kernel@vger.kernel.org, linuxarm@huawei.com, zhangshaokun@hisilicon.com, sanil.kumar@hisilicon.com, linux-arm-kernel@lists.infradead.org, shiju.jose@huawei.com, tanxiaojun@huawei.com, anurup.m@huawei.com MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP 1. Add nodes for hip06 L3 cache to support uncore events. 2. Add nodes for hip06 MN to support uncore events. Signed-off-by: Shaokun Zhang Signed-off-by: John Garry Signed-off-by: Anurup M --- arch/arm64/boot/dts/hisilicon/hip06.dtsi | 78 ++++++++++++++++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi index e861698..309b974 100644 --- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi @@ -963,6 +963,84 @@ status = "disabled"; }; + djtag0: djtag@60010000 { + compatible = "hisilicon,hisi-djtag-v1"; + reg = <0x0 0x60010000 0x0 0x10000>; + scl-id = <0x02>; + + /* L3 cache bank 0 for socket0 CPU die scl#2 */ + pmul3c0 { + compatible = "hisilicon,hisi-pmu-l3c-v1"; + module-id = <0x04 0x02>; + }; + + /* L3 cache bank 1 for socket0 CPU die scl#2 */ + pmul3c1 { + compatible = "hisilicon,hisi-pmu-l3c-v1"; + module-id = <0x04 0x04>; + }; + + /* L3 cache bank 2 for socket0 CPU die scl#2 */ + pmul3c2 { + compatible = "hisilicon,hisi-pmu-l3c-v1"; + module-id = <0x04 0x01>; + }; + + /* L3 cache bank 3 for socket0 CPU die scl#2 */ + pmul3c3 { + compatible = "hisilicon,hisi-pmu-l3c-v1"; + module-id = <0x04 0x08>; + }; + + /* + * Miscellaneous node for socket0 + * CPU die scl#2 + */ + pmumn0 { + compatible = "hisilicon,hisi-pmu-mn-v1"; + module-id = <0x0b>; + }; + }; + + djtag1: djtag@40010000 { + compatible = "hisilicon,hisi-djtag-v1"; + reg = <0x0 0x40010000 0x0 0x10000>; + scl-id = <0x01>; + + /* L3 cache bank 0 for socket0 CPU die scl#1 */ + pmul3c0 { + compatible = "hisilicon,hisi-pmu-l3c-v1"; + module-id = <0x04 0x02>; + }; + + /* L3 cache bank 1 for socket0 CPU die scl#1 */ + pmul3c1 { + compatible = "hisilicon,hisi-pmu-l3c-v1"; + module-id = <0x04 0x04>; + }; + + /* L3 cache bank 2 for socket0 CPU die scl#1 */ + pmul3c2 { + compatible = "hisilicon,hisi-pmu-l3c-v1"; + module-id = <0x04 0x01>; + }; + + /* L3 cache bank 3 for socket0 CPU die scl#1 */ + pmul3c3 { + compatible = "hisilicon,hisi-pmu-l3c-v1"; + module-id = <0x04 0x08>; + }; + + /* + * Miscellaneous node for socket0 + * CPU die scl#1 + */ + pmumn1 { + compatible = "hisilicon,hisi-pmu-mn-v1"; + module-id = <0x0b>; + }; + }; + sas1: sas@a2000000 { compatible = "hisilicon,hip06-sas-v2"; reg = <0 0xa2000000 0 0x10000>;