From patchwork Fri Dec 9 14:15:14 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 9468293 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7DCCE60586 for ; Fri, 9 Dec 2016 14:19:33 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6E70E28619 for ; Fri, 9 Dec 2016 14:19:33 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 615BA2861F; Fri, 9 Dec 2016 14:19:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 153C128619 for ; Fri, 9 Dec 2016 14:19:33 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1cFLz8-00016a-SA; Fri, 09 Dec 2016 14:17:14 +0000 Received: from mail-wm0-x22b.google.com ([2a00:1450:400c:c09::22b]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1cFLyg-0000wT-Up for linux-arm-kernel@lists.infradead.org; Fri, 09 Dec 2016 14:16:48 +0000 Received: by mail-wm0-x22b.google.com with SMTP id a197so28325799wmd.0 for ; Fri, 09 Dec 2016 06:16:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=YR9Vb5HGJUjpifr3Uk6lzKwcbSkDrS+IMPspec3oD08=; b=eCaDL5d93xx9PMaJDBQGfOzMpXvSLjAr4AOGrD/K4XDyp84W4JUs6IsEeTZ/TkDENm S5SFWQw9VKWSDhc1WLJTXcKQxQRXe7/IJJXaTVTvBLQHUYMx+n7kjhvCBcgHzf0TzbY/ ObukDIqJzWfC8UMnb0UqY/PxCToRvqN7Ocub4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=YR9Vb5HGJUjpifr3Uk6lzKwcbSkDrS+IMPspec3oD08=; b=UZ6MNQMiM/NWRNW81it4SNRD1V7zD/YplJeCjYFx83JxndRqXAd889msw4wf9KaiQU vEh6K5wJ+ef9cJp3rgbTRGpIl/TfSCm8F6NHvzIszI5XvRCPSXhZpZPIEZWgKZlE2Jl7 dLLGWSI0lFBSjZLp+2OV7iIMbJtdQZzMscy6KF06yLvQyhkwQXZ8Tkukln79c9VyVY/U XFlZVQ4oUWlCNsyKpP0sMyJSUs2U2GCqLYdPvz87U+vNnMLjoGxbkyyygICRh1QPADwb DCmMrnuISW7RtEWsmYls3PC3FFBOKDMmtFY3TfMlYGYz8g1gNzo+CszOkwvNsO/VShSI rRKA== X-Gm-Message-State: AKaTC00hnBdQP7VWiZntfkFPfCY/h8zJwJ6XtP0F9KyiPmKH7boVWTliBDHOYRTc3g+RjkO/ X-Received: by 10.28.105.81 with SMTP id e78mr7502673wmc.140.1481292984949; Fri, 09 Dec 2016 06:16:24 -0800 (PST) Received: from lmenx321.st.com. ([80.215.96.58]) by smtp.gmail.com with ESMTPSA id j6sm42589344wjk.25.2016.12.09.06.16.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Dec 2016 06:16:24 -0800 (PST) From: Benjamin Gaignard X-Google-Original-From: Benjamin Gaignard To: lee.jones@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, alexandre.torgue@st.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, thierry.reding@gmail.com, linux-pwm@vger.kernel.org, jic23@kernel.org, knaack.h@gmx.de, lars@metafoo.de, pmeerw@pmeerw.net, linux-iio@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v6 3/8] PWM: add pwm-stm32 DT bindings Date: Fri, 9 Dec 2016 15:15:14 +0100 Message-Id: <1481292919-26587-4-git-send-email-benjamin.gaignard@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1481292919-26587-1-git-send-email-benjamin.gaignard@st.com> References: <1481292919-26587-1-git-send-email-benjamin.gaignard@st.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20161209_061647_292966_B58C1D47 X-CRM114-Status: GOOD ( 13.32 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linaro-kernel@lists.linaro.org, Benjamin Gaignard , linus.walleij@linaro.org, arnaud.pouliquen@st.com, benjamin.gaignard@linaro.org, gerald.baeza@st.com, fabrice.gasnier@st.com MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Define bindings for pwm-stm32 version 6: - change st,breakinput parameter format to make it usuable on stm32f7 too. version 2: - use parameters instead of compatible of handle the hardware configuration Signed-off-by: Benjamin Gaignard Acked-by: Rob Herring --- .../devicetree/bindings/pwm/pwm-stm32.txt | 33 ++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/pwm-stm32.txt diff --git a/Documentation/devicetree/bindings/pwm/pwm-stm32.txt b/Documentation/devicetree/bindings/pwm/pwm-stm32.txt new file mode 100644 index 0000000..866f222 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/pwm-stm32.txt @@ -0,0 +1,33 @@ +STMicroelectronics STM32 Timers PWM bindings + +Must be a sub-node of an STM32 Timers device tree node. +See ../mfd/stm32-timers.txt for details about the parent node. + +Required parameters: +- compatible: Must be "st,stm32-pwm". +- pinctrl-names: Set to "default". +- pinctrl-0: List of phandles pointing to pin configuration nodes for PWM module. + For Pinctrl properties see ../pinctrl/pinctrl-bindings.txt + +Optional parameters: +- st,breakinput: Arrays of three u32 to describe break input configurations. + "index" indicates on which break input the configuration should be applied. + "level" gives the active level (0=low or 1=high) for this configuration. + "filter" gives the filtering value to be applied. + +Example: + timers@40010000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40010000 0x400>; + clocks = <&rcc 0 160>; + clock-names = "clk_int"; + + pwm { + compatible = "st,stm32-pwm"; + pinctrl-0 = <&pwm1_pins>; + pinctrl-names = "default"; + st,breakinput = <0 1 5>; + }; + };