From patchwork Thu Jan 5 11:07:55 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 9498879 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 2757960413 for ; Thu, 5 Jan 2017 11:09:10 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 465F11FE82 for ; Thu, 5 Jan 2017 11:09:10 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3AC41282E8; Thu, 5 Jan 2017 11:09:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B610C1FE82 for ; Thu, 5 Jan 2017 11:09:09 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1cP5ut-0005Ha-4D; Thu, 05 Jan 2017 11:09:07 +0000 Received: from mail-wm0-x22a.google.com ([2a00:1450:400c:c09::22a]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1cP5ua-0004am-74 for linux-arm-kernel@lists.infradead.org; Thu, 05 Jan 2017 11:08:50 +0000 Received: by mail-wm0-x22a.google.com with SMTP id a197so429420318wmd.0 for ; Thu, 05 Jan 2017 03:08:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2UQjm5eF5gysc0W9gEqWfXw+xy0f65FoT4CoqqhYM7g=; b=B/lBfVpsQPdozkI14IUpU6cjydwSCFUts5u6VlVmfsCf0nQT3XLO76lyV7mkyTIL1K boCIzjQ95EMK3jxKI+A9e+THTZulJCqOE+zyjkirFsIsjSqU5dezrqOo1YZoTHS/upAc 7cXSMrZeZxyToznMGFvsRS8EkHFEVsCWwb1/k= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=2UQjm5eF5gysc0W9gEqWfXw+xy0f65FoT4CoqqhYM7g=; b=awHSh8/mMQVgouM7NlF2OtzUlMbWjjc/C9JtH7eqRnn9WnAq/brIONORuJV9kWpB7I e2m1/M7y3rXQAc/qVdBqAfY8eAQOxsskqBrxO7d8rQVwhzE8ZNLLmakzMuu1wFBzyAXX RNFJWysxKidZy0b+zn9GJi/2OFWpMEZ+d2jc5RUiuUJxl5PpIafxdmoK5561inFHVBea 6XHwp85yuSzWB7mksCOXpNPZwSrv0nyAtaeQPYmy+8E0YL8N4HfHqMlKEeyijV6Sl/J0 w6D1MsUO9USGEeTNZJK3U7VxUB8eep5TLqGGhBRGOnN86xcSfl4YPtCguz1NNNP72RZ7 A6BQ== X-Gm-Message-State: AIkVDXIsDEtY89kyJQPbak3t4R40LbWVskG+455dOAvfFhAUB18XrvHPtKepiobQMlrIHbd+ X-Received: by 10.223.161.68 with SMTP id r4mr20141wrr.73.1483614506223; Thu, 05 Jan 2017 03:08:26 -0800 (PST) Received: from anup-HP-Compaq-8100-Elite-CMT-PC.dhcp.avagotech.net ([192.19.237.250]) by smtp.gmail.com with ESMTPSA id x140sm99714260wme.19.2017.01.05.03.08.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 05 Jan 2017 03:08:25 -0800 (PST) From: Anup Patel To: Jassi Brar , Rob Herring Subject: [PATCH v4 2/2] dt-bindings: Add DT bindings info for FlexRM ring manager Date: Thu, 5 Jan 2017 16:37:55 +0530 Message-Id: <1483614475-3442-3-git-send-email-anup.patel@broadcom.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1483614475-3442-1-git-send-email-anup.patel@broadcom.com> References: <1483614475-3442-1-git-send-email-anup.patel@broadcom.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170105_030848_466904_36D72053 X-CRM114-Status: GOOD ( 15.90 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Anup Patel , Scott Branden , Ray Jui , linux-kernel@vger.kernel.org, Pramod KUMAR , bcm-kernel-feedback-list@broadcom.com, Rob Rice , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds device tree bindings document for the FlexRM ring manager found on Broadcom iProc SoCs. Reviewed-by: Ray Jui Reviewed-by: Scott Branden Signed-off-by: Anup Patel Acked-by: Rob Herring --- .../bindings/mailbox/brcm,iproc-flexrm-mbox.txt | 59 ++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/brcm,iproc-flexrm-mbox.txt diff --git a/Documentation/devicetree/bindings/mailbox/brcm,iproc-flexrm-mbox.txt b/Documentation/devicetree/bindings/mailbox/brcm,iproc-flexrm-mbox.txt new file mode 100644 index 0000000..752ae6b --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/brcm,iproc-flexrm-mbox.txt @@ -0,0 +1,59 @@ +Broadcom FlexRM Ring Manager +============================ +The Broadcom FlexRM ring manager provides a set of rings which can be +used to submit work to offload engines. An SoC may have multiple FlexRM +hardware blocks. There is one device tree entry per FlexRM block. The +FlexRM driver will create a mailbox-controller instance for given FlexRM +hardware block where each mailbox channel is a separate FlexRM ring. + +Required properties: +-------------------- +- compatible: Should be "brcm,iproc-flexrm-mbox" +- reg: Specifies base physical address and size of the FlexRM + ring registers +- msi-parent: Phandles (and potential Device IDs) to MSI controllers + The FlexRM engine will send MSIs (instead of wired + interrupts) to CPU. There is one MSI for each FlexRM ring. + Refer devicetree/bindings/interrupt-controller/msi.txt +- #mbox-cells: Specifies the number of cells needed to encode a mailbox + channel. This should be 3. + + The 1st cell is the mailbox channel number. + + The 2nd cell contains MSI completion threshold. This is the + number of completion messages for which FlexRM will inject + one MSI interrupt to CPU. + + The 3nd cell contains MSI timer value representing time for + which FlexRM will wait to accumulate N completion messages + where N is the value specified by 2nd cell above. If FlexRM + does not get required number of completion messages in time + specified by this cell then it will inject one MSI interrupt + to CPU provided atleast one completion message is available. + +Optional properties: +-------------------- +- dma-coherent: Present if DMA operations made by the FlexRM engine (such + as DMA descriptor access, access to buffers pointed by DMA + descriptors and read/write pointer updates to DDR) are + cache coherent with the CPU. + +Example: +-------- +crypto_mbox: mbox@67000000 { + compatible = "brcm,iproc-flexrm-mbox"; + reg = <0x67000000 0x200000>; + msi-parent = <&gic_its 0x7f00>; + #mbox-cells = <3>; +}; + +crypto@672c0000 { + compatible = "brcm,spu2-v2-crypto"; + reg = <0x672c0000 0x1000>; + mboxes = <&crypto_mbox 0 0x1 0xffff>, + <&crypto_mbox 1 0x1 0xffff>, + <&crypto_mbox 16 0x1 0xffff>, + <&crypto_mbox 17 0x1 0xffff>, + <&crypto_mbox 30 0x1 0xffff>, + <&crypto_mbox 31 0x1 0xffff>; +};