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[86.31.179.135]) by smtp.gmail.com with ESMTPSA id 202sm30001663wmp.20.2017.01.17.08.46.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 17 Jan 2017 08:46:59 -0800 (PST) From: Peter Griffin To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@stlinux.com, patrice.chotard@st.com Subject: [PATCH] ARM: DT: STiH407: Add RTS / CTS pinctrl definition for UARTs. Date: Tue, 17 Jan 2017 16:46:55 +0000 Message-Id: <1484671615-16343-1-git-send-email-peter.griffin@linaro.org> X-Mailer: git-send-email 2.7.4 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170117_084723_431858_CA894286 X-CRM114-Status: UNSURE ( 9.43 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.griffin@linaro.org, lee.jones@linaro.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The uart IP is capable of doing hardware flow control. Define the RTS and CTS pins for STiH407 family Socs so we can use this feature in the future if we wish to. Signed-off-by: Peter Griffin --- arch/arm/boot/dts/stih407-pinctrl.dtsi | 50 ++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/stih407-pinctrl.dtsi index daab16b..3bbb0c0 100644 --- a/arch/arm/boot/dts/stih407-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih407-pinctrl.dtsi @@ -149,6 +149,16 @@ rx = <&pio3 5 ALT1 IN>; }; }; + pinctrl_sbc_serial0_rts: sbc_serial0-0_rts { + st,pins { + rts = <&pio3 7 ALT1 OUT>; + }; + }; + pinctrl_sbc_serial0_cts: sbc_serial0-0_cts { + st,pins { + cts = <&pio3 6 ALT1 IN>; + }; + }; }; /* SBC_ASC1 - UART11 */ sbc_serial1 { @@ -158,6 +168,16 @@ rx = <&pio2 7 ALT3 IN>; }; }; + pinctrl_sbc_serial1_rts: sbc_serial1-0_rts { + st,pins { + rts = <&pio3 1 ALT3 OUT>; + }; + }; + pinctrl_sbc_serial1_cts: sbc_serial1-0_cts { + st,pins { + cts = <&pio3 0 ALT3 IN>; + }; + }; }; i2c10 { @@ -469,6 +489,16 @@ rx = <&pio17 1 ALT1 IN>; }; }; + pinctrl_serial0_rts: serial0-0_rts { + st,pins { + rts = <&pio17 3 ALT1 OUT>; + }; + }; + pinctrl_serial0_cts: serial0-0_cts { + st,pins { + cts = <&pio17 2 ALT1 IN>; + }; + }; }; serial1 { @@ -478,6 +508,16 @@ rx = <&pio16 1 ALT1 IN>; }; }; + pinctrl_serial1_rts: serial1-0_rts { + st,pins { + rts = <&pio16 3 ALT1 OUT>; + }; + }; + pinctrl_serial1_cts: serial1-0_cts { + st,pins { + cts = <&pio16 2 ALT1 IN>; + }; + }; }; serial2 { @@ -487,6 +527,16 @@ rx = <&pio15 1 ALT1 IN>; }; }; + pinctrl_serial2_rts: serial2-0_rts { + st,pins { + rts = <&pio15 3 ALT1 OUT>; + }; + }; + pinctrl_serial2_cts: serial2-0_cts { + st,pins { + cts = <&pio15 2 ALT1 IN>; + }; + }; }; mmc1 {