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([37.161.107.133]) by smtp.gmail.com with ESMTPSA id z134sm53175373wmc.20.2017.01.19.05.26.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 19 Jan 2017 05:26:10 -0800 (PST) From: M'boumba Cedric Madianga To: wsa@the-dreams.de, robh+dt@kernel.org, mcoquelin.stm32@gmail.com, alexandre.torgue@st.com, linus.walleij@linaro.org, patrice.chotard@st.com, linux@armlinux.org.uk, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, u.kleine-koenig@pengutronix.de Subject: [PATCH v10 3/5] ARM: dts: stm32: Add I2C1 support for STM32F429 SoC Date: Thu, 19 Jan 2017 14:25:14 +0100 Message-Id: <1484832316-5594-4-git-send-email-cedric.madianga@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1484832316-5594-1-git-send-email-cedric.madianga@gmail.com> References: <1484832316-5594-1-git-send-email-cedric.madianga@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170119_052733_971392_5636484A X-CRM114-Status: GOOD ( 10.96 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: M'boumba Cedric Madianga MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds I2C1 support for STM32F429 SoC Signed-off-by: Patrice Chotard Signed-off-by: M'boumba Cedric Madianga --- arch/arm/boot/dts/stm32f429.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index e4dae0e..5b063e9 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -48,6 +48,7 @@ #include "skeleton.dtsi" #include "armv7-m.dtsi" #include +#include / { clocks { @@ -153,6 +154,18 @@ status = "disabled"; }; + i2c1: i2c@40005400 { + compatible = "st,stm32f4-i2c"; + reg = <0x40005400 0x400>; + interrupts = <31>, + <32>; + resets = <&rcc STM32F4_APB1_RESET(I2C1)>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + usart7: serial@40007800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40007800 0x400>; @@ -355,6 +368,16 @@ slew-rate = <2>; }; }; + + i2c1_pins_b: i2c1@0 { + pins { + pinmux = , + ; + bias-disable; + drive-open-drain; + slew-rate = <3>; + }; + }; }; rcc: rcc@40023810 {