From patchwork Mon Jan 23 22:32:45 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 9533677 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 8861A6042F for ; Mon, 23 Jan 2017 22:36:21 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7AB9127D29 for ; Mon, 23 Jan 2017 22:36:21 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6FB272836D; Mon, 23 Jan 2017 22:36:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=2.0 tests=BAYES_00 autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 2F00727D29 for ; Mon, 23 Jan 2017 22:36:21 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1cVnDc-0004mz-N3; Mon, 23 Jan 2017 22:36:08 +0000 Received: from foss.arm.com ([217.140.101.70]) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1cVnB5-0001c3-Mx for linux-arm-kernel@lists.infradead.org; Mon, 23 Jan 2017 22:33:33 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 44D6F1682; Mon, 23 Jan 2017 14:32:50 -0800 (PST) Received: from beelzebub.ast.arm.com (unknown [10.118.96.220]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id B9C6A3F318; Mon, 23 Jan 2017 14:32:49 -0800 (PST) From: Jeremy Linton To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v14 6/6] arm: pmu: Add PMU definitions for cores not initially online Date: Mon, 23 Jan 2017 16:32:45 -0600 Message-Id: <1485210765-9422-7-git-send-email-jeremy.linton@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1485210765-9422-1-git-send-email-jeremy.linton@arm.com> References: <1485210765-9422-1-git-send-email-jeremy.linton@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170123_143331_874341_8CEC5D9F X-CRM114-Status: GOOD ( 13.23 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, lorenzo.pieralisi@arm.com, steve.capper@arm.com, mlangsdorf@redhat.com, punit.agrawal@arm.com, will.deacon@arm.com, linux@armlinux.org.uk, linux-acpi@vger.kernel.org, msalter@redhat.com, bamvor.zhangjian@linaro.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP ACPI CPUs aren't associated with a PMU until they have been put online. This means that we potentially have to update a PMU definition the first time a CPU is hot added to the machine. Signed-off-by: Jeremy Linton --- drivers/perf/arm_pmu.c | 34 ++++++++++++++++++++++++++++++++-- include/linux/perf/arm_pmu.h | 4 ++++ 2 files changed, 36 insertions(+), 2 deletions(-) diff --git a/drivers/perf/arm_pmu.c b/drivers/perf/arm_pmu.c index 77ec1ae..cf5122f 100644 --- a/drivers/perf/arm_pmu.c +++ b/drivers/perf/arm_pmu.c @@ -711,6 +711,26 @@ static int cpu_pmu_request_irq(struct arm_pmu *cpu_pmu, irq_handler_t handler) return 0; } +static void arm_perf_associate_new_cpu(struct arm_pmu *lpmu, unsigned int cpu) +{ + struct platform_device *pdev = lpmu->plat_device; + struct resource *res; + struct pmu_hw_events *events; + int num_res; + + for (num_res = 0; num_res < pdev->num_resources; num_res++) { + if (!pdev->resource[num_res].flags) + break; + } + res = &pdev->resource[num_res]; + arm_pmu_acpi_retrieve_irq(res, cpu); + events = per_cpu_ptr(lpmu->hw_events, cpu); + cpumask_set_cpu(cpu, &lpmu->supported_cpus); + if (lpmu->irq_affinity) + lpmu->irq_affinity[num_res] = cpu; + events->percpu_pmu = lpmu; +} + /* * PMU hardware loses all context when a CPU goes offline. * When a CPU is hotplugged back in, since some hardware registers are @@ -721,10 +741,18 @@ static int arm_perf_starting_cpu(unsigned int cpu, struct hlist_node *node) { struct arm_pmu *pmu = hlist_entry_safe(node, struct arm_pmu, node); - if (!cpumask_test_cpu(cpu, &pmu->supported_cpus)) - return 0; + if (!cpumask_test_cpu(cpu, &pmu->supported_cpus)) { + unsigned int cpuid = read_specific_cpuid(cpu); + + if (acpi_disabled) + return 0; + if (cpuid != pmu->id) + return 0; + arm_perf_associate_new_cpu(pmu, cpu); + } if (pmu->reset) pmu->reset(pmu); + return 0; } @@ -905,6 +933,8 @@ static int probe_plat_pmu(struct arm_pmu *pmu, struct platform_device *pdev = pmu->plat_device; int irq = platform_get_irq(pdev, 0); + pmu->id = pmuid; + if (irq >= 0 && !irq_is_percpu(irq)) { pmu->irq_affinity = kcalloc(pdev->num_resources, sizeof(int), GFP_KERNEL); diff --git a/include/linux/perf/arm_pmu.h b/include/linux/perf/arm_pmu.h index 42b5edb..f652cd1 100644 --- a/include/linux/perf/arm_pmu.h +++ b/include/linux/perf/arm_pmu.h @@ -112,6 +112,7 @@ struct arm_pmu { struct mutex reserve_mutex; u64 max_period; bool secure_access; /* 32-bit ARM only */ + unsigned int id; #define ARMV8_PMUV3_MAX_COMMON_EVENTS 0x40 DECLARE_BITMAP(pmceid_bitmap, ARMV8_PMUV3_MAX_COMMON_EVENTS); struct platform_device *plat_device; @@ -168,8 +169,11 @@ int arm_pmu_device_probe(struct platform_device *pdev, #ifdef CONFIG_ARM_PMU_ACPI struct acpi_madt_generic_interrupt; void arm_pmu_parse_acpi(int cpu, struct acpi_madt_generic_interrupt *gic); +int arm_pmu_acpi_retrieve_irq(struct resource *pdev, int cpu); #else #define arm_pmu_parse_acpi(a, b) do { } while (0) +#define arm_pmu_acpi_retrieve_irq(pdev, cpu) \ + do { } while (0) #endif /* CONFIG_ARM_PMU_ACPI */ #endif /* __ARM_PMU_H__ */