From patchwork Mon Feb 6 02:17:45 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shanker Donthineni X-Patchwork-Id: 9557031 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id C8D5460424 for ; Mon, 6 Feb 2017 02:18:51 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AEFE4204C1 for ; Mon, 6 Feb 2017 02:18:51 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9F88B26C9B; Mon, 6 Feb 2017 02:18:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, T_DKIM_INVALID autolearn=no version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 180CE204C1 for ; Mon, 6 Feb 2017 02:18:51 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1caYtE-0000UA-BT; Mon, 06 Feb 2017 02:18:48 +0000 Received: from smtp.codeaurora.org ([198.145.29.96]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1caYt8-0000R2-Iv for linux-arm-kernel@lists.infradead.org; Mon, 06 Feb 2017 02:18:46 +0000 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id CF63060A60; Mon, 6 Feb 2017 02:18:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1486347501; bh=lBWDCQ4m/jP06usf/XI5IRFbQXkCx/jBWjTVE98UzFk=; h=From:To:Cc:Subject:Date:From; b=QRDpScUo4wPhZDaQO2JVltqLTwbRWqZuFSz22J4sAEFHBnO3nU94TGCLTxhFzynfi l8zLhHpHwqfka/O8LAScvLwoDro2pDnKJ8qORc0lms+NjhHMJsRGwkUlwO1scJvsfT LWgQbRYpXx2Dw9BFdo9lY+N8UeUeeFaLz7B8Ug+g= Received: from shankerd-ubuntu.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: shankerd@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id E05E860A54; Mon, 6 Feb 2017 02:18:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1486347500; bh=lBWDCQ4m/jP06usf/XI5IRFbQXkCx/jBWjTVE98UzFk=; h=From:To:Cc:Subject:Date:From; b=WamPLxKqnIlgf1GKVl6SXjLS6Wz0AlxEIXCib1iop7Nfra+Wdoh4U+bFPsiHBVW6L hoNjFVG+a5WSoO4FZRj6pHHsNtYXrLxkVLftPyHF807GSiTL5Izch3BolgZMO6yMJT WFXynXY/OM2xTlvbWQFp4CA7/4JgRL3fw60S4CWQ= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org E05E860A54 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=shankerd@codeaurora.org From: Shanker Donthineni To: Marc Zyngier , linux-kernel , linux-arm-kernel Subject: [PATCH] irqchip/gicv3: Fix GICR_WAKE & GICD_IGROUPR accesses from non-secure Date: Sun, 5 Feb 2017 20:17:45 -0600 Message-Id: <1486347465-28316-1-git-send-email-shankerd@codeaurora.org> X-Mailer: git-send-email 1.9.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170205_181842_670369_EF7165EE X-CRM114-Status: GOOD ( 18.33 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Vikram Sethi , Thomas Gleixner , Shanker Donthineni , Jason Cooper , Christoffer Dall MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP On systems where it supports two security states, both the register GICR_WAKE and GICD_IGROUPR accesses are RAZ/WI from non-secure. The function gic_enable_redist() to wake/sleep redistributor is not harmful at all, but it is confusing looking at the code. The current code checks the single security state based on bit GICD_CTLR.DS which is absolutely incorrect. The disable security bit GICD_CTLR.DS is RAZ to non-secure. The GICD_TYPE.SecurityExtn indicates whether the GIC implementation supports two security states or only one security state. Let's introduce a new helper function gic_has_security_extn() to know GIC security state. Use this function to bypass the code that is touching the registers GICR_WAKE and GICD_IGROUPR. Signed-off-by: Shanker Donthineni --- drivers/irqchip/irq-gic-v3.c | 36 +++++++++++++++++++++++++++--------- include/linux/irqchip/arm-gic-v3.h | 1 + 2 files changed, 28 insertions(+), 9 deletions(-) diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index c132f29..a66002c 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -130,12 +130,28 @@ static u64 __maybe_unused gic_read_iar(void) } #endif +/** + * Check whether the GIC implementation supports two security + * states or only one security state. + * return true if it has two security states else return false. + */ +static bool gic_has_security_extn(void) +{ + u32 typer = readl_relaxed(gic_data.dist_base + GICD_TYPER); + + return !!(typer & GICD_TYPER_SECURITY_EXTN); +} + static void gic_enable_redist(bool enable) { void __iomem *rbase; u32 count = 1000000; /* 1s! */ u32 val; + /* With only one security state, GICR_WAKE is RAZ/WI to non-secure */ + if (gic_has_security_extn()) + return; + rbase = gic_data_rdist_rd_base(); val = readl_relaxed(rbase + GICR_WAKER); @@ -397,16 +413,18 @@ static void __init gic_dist_init(void) writel_relaxed(0, base + GICD_CTLR); gic_dist_wait_for_rwp(); - /* - * Configure SPIs as non-secure Group-1. This will only matter - * if the GIC only has a single security state. This will not - * do the right thing if the kernel is running in secure mode, - * but that's not the intended use case anyway. - */ - for (i = 32; i < gic_data.irq_nr; i += 32) - writel_relaxed(~0, base + GICD_IGROUPR + i / 8); + if (!gic_has_security_extn()) { + /* + * Configure SPIs as non-secure Group-1. This will only matter + * if the GIC only has a single security state. This will not + * do the right thing if the kernel is running in secure mode, + * but that's not the intended use case anyway. + */ + for (i = 32; i < gic_data.irq_nr; i += 32) + writel_relaxed(~0, base + GICD_IGROUPR + i / 8); - gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp); + gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp); + } /* Enable distributor with ARE, Group1 */ writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1, diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h index e808f8a..aab00e5 100644 --- a/include/linux/irqchip/arm-gic-v3.h +++ b/include/linux/irqchip/arm-gic-v3.h @@ -70,6 +70,7 @@ #define GICD_TYPER_LPIS (1U << 17) #define GICD_TYPER_MBIS (1U << 16) +#define GICD_TYPER_SECURITY_EXTN (1U << 10) #define GICD_TYPER_ID_BITS(typer) ((((typer) >> 19) & 0x1f) + 1) #define GICD_TYPER_IRQS(typer) ((((typer) & 0x1f) + 1) * 32)