From patchwork Tue Feb 21 14:09:55 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shanker Donthineni X-Patchwork-Id: 9584675 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 9374E600C1 for ; Tue, 21 Feb 2017 14:11:18 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 87B46288EA for ; Tue, 21 Feb 2017 14:11:18 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7C77A288EF; Tue, 21 Feb 2017 14:11:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id C3F53288EA for ; Tue, 21 Feb 2017 14:11:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To: References:List-Owner; bh=+Ou6LIGOaibvTJYM4yiQGf6iedu9pkLf6r3hCRpjTpA=; b=Gbk q9PsxLNDRAsYs45MvnwIZ/Rpm3j3vT3bwfEQgQN/fgHYCPMbkiT2ed4J95bmaXzBVACqhu2CC7l8q Ba11sAmZ8pCmKGHXsU1d8E0Gqo4WLACxSWJFM5TTcS3UeFw+wHwKde89vjSrpyXIDMW/Gm9Zf8BQQ lkILY4xQC8haN3sheOFli4oAKwXF/SExVbVYR8InsqwDiRAy8pBzyavHiv6a7G4Xv8Vy6TRDNYrOS UL3yjsrRboTDXBG0h5RJTRhnTQrV7ch8RNWpcC6G8I4AqqCevgP+pJOw+1QcUdo3p0cu90xVvpBTE H2nb+HSNUttTZrG97q+YY6EBRRbpbIw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1cgB9n-0006HH-HL; Tue, 21 Feb 2017 14:11:07 +0000 Received: from smtp.codeaurora.org ([198.145.29.96]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1cgB9M-0006ET-97 for linux-arm-kernel@lists.infradead.org; Tue, 21 Feb 2017 14:10:42 +0000 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 968B060B66; Tue, 21 Feb 2017 14:10:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1487686219; bh=q1Wu1JJ07PSNrthe13CnnxN2RIEcky5MPiznnXVxBSs=; h=From:To:Cc:Subject:Date:From; b=TXkRzYuK/9U1AJHQMXZDWDgzjCfYCgr0XIvmNfvAMyYUJFyQ7TvJy13Ro3zvpCkvh xG+gAQocPoDb7ygVuHMRFwKRlRpXXQgqaQWwp0NmV0AP4bVhfP6sTofbBvwUwHgMch /16DXjDn2KeniyZZ9uDEwstZIfPQP0nonj587dqI= Received: from shankerd-ubuntu.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: shankerd@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 4F84C60A7F; Tue, 21 Feb 2017 14:10:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1487686219; bh=q1Wu1JJ07PSNrthe13CnnxN2RIEcky5MPiznnXVxBSs=; h=From:To:Cc:Subject:Date:From; b=TXkRzYuK/9U1AJHQMXZDWDgzjCfYCgr0XIvmNfvAMyYUJFyQ7TvJy13Ro3zvpCkvh xG+gAQocPoDb7ygVuHMRFwKRlRpXXQgqaQWwp0NmV0AP4bVhfP6sTofbBvwUwHgMch /16DXjDn2KeniyZZ9uDEwstZIfPQP0nonj587dqI= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 4F84C60A7F Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=shankerd@codeaurora.org From: Shanker Donthineni To: Catalin Marinas Subject: [RESEND PATCH] arm64: Add support for VMID aware PIPT instruction cache Date: Tue, 21 Feb 2017 08:09:55 -0600 Message-Id: <1487686195-16282-1-git-send-email-shankerd@codeaurora.org> X-Mailer: git-send-email 1.9.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170221_061040_497462_2956C341 X-CRM114-Status: GOOD ( 13.98 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Vikram Sethi , Suzuki K Poulose , Marc Zyngier , Will Deacon , linux-kernel , James Morse , Shanker Donthineni , Anna-Maria Gleixner , linux-arm-kernel MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP In ARMv8.2 extension, a new instruction cache type 'VMID aware PIPT' was introduced in addition to AIVIVT/VIPT/PIPT. Instruction cache maintenance operations when issued from Non-secure EL1/EL0 have an effect only on cache line entries those were fetched in Non-secure EL1/EL0 using the current VMID. For software point of view, this cache type is same as PIPT and no aliasing problem. The updated CTR_EL0.L1IP definition. 00: VMID aware PIPT 01: ASID-tagged Virtual Index, Virtual Tag (AIVIVT) 10: Virtual Index, Physical Tag (VIPT) 11: Physical Index, Physical Tag (PIPT) Signed-off-by: Shanker Donthineni --- arch/arm64/include/asm/cachetype.h | 2 +- arch/arm64/kernel/cpuinfo.c | 9 +++++---- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/arch/arm64/include/asm/cachetype.h b/arch/arm64/include/asm/cachetype.h index f05974c..cb84b4d 100644 --- a/arch/arm64/include/asm/cachetype.h +++ b/arch/arm64/include/asm/cachetype.h @@ -23,7 +23,7 @@ #define CTR_CWG_SHIFT 24 #define CTR_CWG_MASK 15 -#define ICACHE_POLICY_RESERVED 0 +#define ICACHE_POLICY_VPIPT 0 #define ICACHE_POLICY_AIVIVT 1 #define ICACHE_POLICY_VIPT 2 #define ICACHE_POLICY_PIPT 3 diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index 2d52f8d..e2063de 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -43,7 +43,7 @@ static struct cpuinfo_arm64 boot_cpu_data; static char *icache_policy_str[] = { - [ICACHE_POLICY_RESERVED] = "RESERVED/UNKNOWN", + [ICACHE_POLICY_VPIPT] = "VPIPT", [ICACHE_POLICY_AIVIVT] = "AIVIVT", [ICACHE_POLICY_VIPT] = "VIPT", [ICACHE_POLICY_PIPT] = "PIPT", @@ -288,7 +288,7 @@ static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info) unsigned int cpu = smp_processor_id(); u32 l1ip = CTR_L1IP(info->reg_ctr); - if (l1ip != ICACHE_POLICY_PIPT) { + if (l1ip == ICACHE_POLICY_AIVIVT || l1ip == ICACHE_POLICY_VIPT) { /* * VIPT caches are non-aliasing if the VA always equals the PA * in all bit positions that are covered by the index. This is @@ -299,9 +299,10 @@ static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info) if (l1ip != ICACHE_POLICY_VIPT || waysize > PAGE_SIZE) set_bit(ICACHEF_ALIASING, &__icache_flags); + + if (l1ip == ICACHE_POLICY_AIVIVT) + set_bit(ICACHEF_AIVIVT, &__icache_flags); } - if (l1ip == ICACHE_POLICY_AIVIVT) - set_bit(ICACHEF_AIVIVT, &__icache_flags); pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str[l1ip], cpu); }