From patchwork Wed Feb 22 17:10:16 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thor Thayer X-Patchwork-Id: 9587201 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 16C346051E for ; Wed, 22 Feb 2017 17:12:10 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 02B37281B7 for ; Wed, 22 Feb 2017 17:12:10 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id EB32526419; Wed, 22 Feb 2017 17:12:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 5E0F726419 for ; Wed, 22 Feb 2017 17:12:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=HLW1MCf2myerv+hObWA9iYghbJDiVt2c6vKALQLRqrs=; b=b7RpQgYD+RzXmF1iwcZnT5nHDY 4zgGJq8fg20jp/7VPK0HVwnR1R9gTu+tJ+ZUPZDMjQ/1SywhYFvLPWk+hEOTRD0QROXdVNXl2M1lD A76UViMtoo5V0vjs+dkPF+bJHC7j4o0loxihrp8qBe5zdAPr6ukGAtk6vsu4pXb2KUplKqQTA6S4S ZYllYAJZ/evOkkX/+heKxMJgj9bZf7DTsThTpF3W1YPBOJfoEtKewBs2zu48pbIZ4vwfiEz/NJDFF XBYdoTFQiK/wdUK4zD2QvU8vSV4cRISkLEPCDNrJ58QUicamabsC7sHg3mizhW/hxC9deg7XL7kXy J18eFmOQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1cgaST-0000xz-10; Wed, 22 Feb 2017 17:12:05 +0000 Received: from mga09.intel.com ([134.134.136.24]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1cgaRE-00009w-Rk for linux-arm-kernel@lists.infradead.org; Wed, 22 Feb 2017 17:10:53 +0000 Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 22 Feb 2017 09:08:44 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.35,195,1484035200"; d="scan'208";a="68342491" Received: from tthayer-hp-z620-ubuntu.an.intel.com (HELO tthayer-HP-Z620-Ubuntu.altera.com) ([10.122.105.144]) by fmsmga005.fm.intel.com with ESMTP; 22 Feb 2017 09:08:43 -0800 From: thor.thayer@linux.intel.com To: lee.jones@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, dinguyen@kernel.org, linux@armlinux.org.uk, p.zabel@pengutronix.de Subject: [PATCHv2 2/5] dt-bindings: reset: a10sr: Add Arria10 SR Reset Controller offsets Date: Wed, 22 Feb 2017 11:10:16 -0600 Message-Id: <1487783419-10912-3-git-send-email-thor.thayer@linux.intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1487783419-10912-1-git-send-email-thor.thayer@linux.intel.com> References: <1487783419-10912-1-git-send-email-thor.thayer@linux.intel.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170222_091049_086284_8A697AAA X-CRM114-Status: GOOD ( 13.68 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, thor.thayer@linux.intel.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Thor Thayer The Arria10 System Resource Chip reset controller handles the Arria10 peripheral PHYs. This patch adds the offsets for these PHYs. Signed-off-by: Thor Thayer --- v2 Add NUM_RESETs to altr,rst-mgr-a10sr.h for maximum count. --- MAINTAINERS | 1 + include/dt-bindings/reset/altr,rst-mgr-a10sr.h | 33 ++++++++++++++++++++++++++ 2 files changed, 34 insertions(+) create mode 100644 include/dt-bindings/reset/altr,rst-mgr-a10sr.h diff --git a/MAINTAINERS b/MAINTAINERS index b9af886..4b714bd 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -654,6 +654,7 @@ S: Maintained F: drivers/gpio/gpio-altera-a10sr.c F: drivers/mfd/altera-a10sr.c F: include/linux/mfd/altera-a10sr.h +F: include/dt-bindings/reset/altr,rst-mgr-a10sr.h ALTERA TRIPLE SPEED ETHERNET DRIVER M: Vince Bridgers diff --git a/include/dt-bindings/reset/altr,rst-mgr-a10sr.h b/include/dt-bindings/reset/altr,rst-mgr-a10sr.h new file mode 100644 index 0000000..9855925 --- /dev/null +++ b/include/dt-bindings/reset/altr,rst-mgr-a10sr.h @@ -0,0 +1,33 @@ +/* + * Copyright Intel Corporation (C) 2017. All Rights Reserved + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + * + * Reset binding definitions for Altera Arria10 MAX5 System Resource Chip + * + * Adapted from altr,rst-mgr-a10.h + */ + +#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10SR_H +#define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10SR_H + +/* Peripheral PHY resets */ +#define A10SR_RESET_ENET_HPS 0 +#define A10SR_RESET_PCIE 1 +#define A10SR_RESET_FILE 2 +#define A10SR_RESET_BQSPI 3 +#define A10SR_RESET_USB 4 + +#define A10SR_RESET_NUM 5 + +#endif