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bh=DMOAq1Z9JeJARvTaQuNVHSjd3+9V7yI3ZSZz3m2nKtY=; b=KmY0pBL6CfJLoC8YwDJy7+IR1/F8O2nPE+x9cqpYhDaWp4xc5uCldrcYHdGlrBSar8 9rw27ehM2ueIH7U1IYXPgmIbVBbbjY7lnSTexDWSofGfX6XJP4s3Km+BTudXWbL/2wK6 a4KUA054JWBMGCgDW5OxYE+HnehQf+xBfv1xOQ0JURGBidSg+eh4X6kZUkDuScCq0p7i KbWcBem3EuKGXU342t97dpQQCrJoVVhLbfhugjUxdQCiesXo+Imvy1sV4PrGw3LrPC1V 7URaNVLKC6XFDLZUuOvxrWhlMCchv3gQyShmGTcw+RfyFucuR4cmRB70ZeJc6TipKqGs zYqg== X-Gm-Message-State: AMke39l+UMN354o7HtvBl2T8TjDH9Q+h9GHRONWCX8T+GXWjvvrSbFV4nEKGjgQmb9Kbow== X-Received: by 10.99.120.76 with SMTP id t73mr18579153pgc.149.1489127247384; Thu, 09 Mar 2017 22:27:27 -0800 (PST) Received: from localhost.localdomain ([14.141.5.98]) by smtp.gmail.com with ESMTPSA id 10sm16018357pfs.113.2017.03.09.22.27.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 09 Mar 2017 22:27:26 -0800 (PST) From: Anurup M X-Google-Original-From: Anurup M To: robh+dt@kernel.org, mark.rutland@arm.com, will.deacon@arm.com Subject: [PATCH v6 02/11] dt-bindings: hisi: Add Hisilicon HiP05/06/07 Djtag dts bindings Date: Fri, 10 Mar 2017 01:27:17 -0500 Message-Id: <1489127237-112561-1-git-send-email-anurup.m@huawei.com> X-Mailer: git-send-email 2.1.4 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170309_222748_369279_8CF63D80 X-CRM114-Status: GOOD ( 12.24 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dikshit.n@huawei.com, devicetree@vger.kernel.org, wangkefeng.wang@huawei.com, anurupvasu@gmail.com, gabriele.paoloni@huawei.com, huangdaode@hisilicon.com, john.garry@huawei.com, shyju.pv@huawei.com, linux-kernel@vger.kernel.org, xuwei5@hisilicon.com, linuxarm@huawei.com, zhangshaokun@hisilicon.com, sanil.kumar@hisilicon.com, linux-arm-kernel@lists.infradead.org, shiju.jose@huawei.com, tanxiaojun@huawei.com, anurup.m@huawei.com MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Tan Xiaojun Add Hisilicon HiP05/06/07 Djtag dts bindings for CPU and IO Die Signed-off-by: Tan Xiaojun Signed-off-by: Anurup M Acked-by: Rob Herring --- .../devicetree/bindings/arm/hisilicon/djtag.txt | 51 ++++++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/djtag.txt diff --git a/Documentation/devicetree/bindings/arm/hisilicon/djtag.txt b/Documentation/devicetree/bindings/arm/hisilicon/djtag.txt new file mode 100644 index 0000000..fde5bab --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/djtag.txt @@ -0,0 +1,51 @@ +The Hisilicon Djtag is an independent component which connects with some other +components in the SoC by Debug Bus. The djtag is available in CPU and IO dies +in the chip. The djtag controls access to connecting modules of CPU and IO +dies. +The various connecting components in CPU die (like L3 cache, L3 cache PMU etc.) +are accessed by djtag during real time debugging. In IO die there are connecting +components like RSA. These components appear as devices attached to djtag bus. + +Hisilicon HiP05/06/07 djtag for CPU die +Required properties: + - compatible : The value should be as follows + (a) "hisilicon,hip05-cpu-djtag-v1" for CPU die which use v1 hw in + HiP05 chipset. + (b) "hisilicon,hip06-cpu-djtag-v1" for CPU die which use v1 hw in + HiP06 chipset. + (c) "hisilicon,hip07-cpu-djtag-v2" for CPU die which use v2 hw in + HiP07 chipset. + - reg : Register address and size + - hisilicon,scl-id : The Super Cluster ID for CPU or IO die + +Example 1: Djtag for CPU die in HiP07 + + /* for Hisilicon HiP07 djtag for CPU Die */ + djtag0: djtag@60010000 { + compatible = "hisilicon,hip07-cpu-djtag-v2"; + reg = <0x0 0x60010000 0x0 0x10000>; + hisilicon,scl-id = <0x03>; + + /* All connecting components will appear as child nodes */ + }; + +Hisilicon HiP05/06/07 djtag for IO die +Required properties: + - compatible : The value should be as follows + (a) "hisilicon,hip05-io-djtag-v1" for IO die which use v1 hw in + HiP05 chipset. + (c) "hisilicon,hip06-io-djtag-v2" for IO die which use v2 hw in + HiP06 chipset. + (d) "hisilicon,hip07-io-djtag-v2" for IO die which use v2 hw in + HiP07 chipset + +Example 2: Djtag for IO die in HiP05 + + /* for Hisilicon HiP05 djtag for IO Die */ + djtag1: djtag@d0000000 { + compatible = "hisilicon,hip05-io-djtag-v1"; + reg = <0x0 0xd0000000 0x0 0x10000>; + hisilicon,scl-id = <0x0>; + + /* All connecting components will appear as child nodes */ + };