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Received: from foss.arm.com ([217.140.101.70]) by casper.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1cqhdS-0001wh-Sf for linux-arm-kernel@lists.infradead.org; Wed, 22 Mar 2017 14:53:16 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 96ECA1597; Wed, 22 Mar 2017 07:53:14 -0700 (PDT) Received: from e103592.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 4FDB33F575; Wed, 22 Mar 2017 07:53:13 -0700 (PDT) From: Dave Martin To: linux-arm-kernel@lists.infradead.org Subject: [RFC PATCH v2 23/41] arm64/sve: Move ZEN handling to the common task_fpsimd_load() path Date: Wed, 22 Mar 2017 14:50:53 +0000 Message-Id: <1490194274-30569-24-git-send-email-Dave.Martin@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1490194274-30569-1-git-send-email-Dave.Martin@arm.com> References: <1490194274-30569-1-git-send-email-Dave.Martin@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170322_145315_243807_CFBFDDCA X-CRM114-Status: GOOD ( 17.72 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Florian Weimer , Ard Biesheuvel , Marc Zyngier , Catalin Marinas , Will Deacon , Szabolcs Nagy , Joseph Myers MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Currently, ZEN is handled only in fpsimd_restore_current_state(), which is not sufficient since it applies only in certain situations. Since all the relevant paths call task_fpsimd_load(), this patch moves the ZEN handling there. Signed-off-by: Dave Martin --- arch/arm64/include/asm/thread_info.h | 1 + arch/arm64/kernel/fpsimd.c | 50 ++++++++++++++++++++---------------- 2 files changed, 29 insertions(+), 22 deletions(-) diff --git a/arch/arm64/include/asm/thread_info.h b/arch/arm64/include/asm/thread_info.h index 272c32d..a0f5498 100644 --- a/arch/arm64/include/asm/thread_info.h +++ b/arch/arm64/include/asm/thread_info.h @@ -107,6 +107,7 @@ struct thread_info { #define _TIF_SYSCALL_AUDIT (1 << TIF_SYSCALL_AUDIT) #define _TIF_SYSCALL_TRACEPOINT (1 << TIF_SYSCALL_TRACEPOINT) #define _TIF_SECCOMP (1 << TIF_SECCOMP) +#define _TIF_SVE (1 << TIF_SVE) #define _TIF_UPROBE (1 << TIF_UPROBE) #define _TIF_32BIT (1 << TIF_32BIT) diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c index 260438d..5fb5585 100644 --- a/arch/arm64/kernel/fpsimd.c +++ b/arch/arm64/kernel/fpsimd.c @@ -37,6 +37,9 @@ #define FPEXC_IXF (1 << 4) #define FPEXC_IDF (1 << 7) +/* Forward declarations for local functions used by both SVE and FPSIMD */ +static void task_fpsimd_load(struct task_struct *task); + /* * In order to reduce the number of times the FPSIMD state is needlessly saved * and restored, we need to keep track of two things: @@ -151,18 +154,20 @@ static void sve_to_fpsimd(struct task_struct *task) void do_sve_acc(unsigned int esr, struct pt_regs *regs) { - unsigned long tmp; + if (test_and_set_thread_flag(TIF_SVE)) { + unsigned long tmp; - if (test_and_set_thread_flag(TIF_SVE)) + asm ("mrs %0, cpacr_el1" : "=r" (tmp)); + + printk(KERN_INFO "%s: Strange, ZEN=%u\n", + __func__, (unsigned int)((tmp >> 16) & 3)); BUG(); + } BUG_ON(is_compat_task()); fpsimd_to_sve(current); - - asm ("mrs %0, cpacr_el1" : "=r" (tmp)); - asm volatile ("msr cpacr_el1, %0" :: "r" (tmp | (1 << 17))); - /* Serialised by exception return to user */ + task_fpsimd_load(current); } #else /* ! CONFIG_ARM64_SVE */ @@ -220,6 +225,23 @@ static void task_fpsimd_load(struct task_struct *task) &task->thread.fpsimd_state.fpsr); else fpsimd_load_state(&task->thread.fpsimd_state); + + /* + * Flip SVE enable for userspace if it doesn't match the + * current_task. + */ + if (IS_ENABLED(CONFIG_ARM64_SVE) && (elf_hwcap & HWCAP_SVE)) { + unsigned int tmp, flags; + + asm ("mrs %0, cpacr_el1" : "=r" (tmp)); + flags = task_thread_info(task)->flags; + BUILD_BUG_ON(_TIF_SVE != CPACR_EL1_ZEN_EL0EN); + if ((tmp ^ (unsigned long)flags) & _TIF_SVE) { + tmp ^= _TIF_SVE; + asm volatile ("msr cpacr_el1, %0" :: "r" (tmp)); + /* Serialised by exception return to user */ + } + } } static void task_fpsimd_save(struct task_struct *task) @@ -323,27 +345,11 @@ void fpsimd_restore_current_state(void) return; preempt_disable(); if (test_and_clear_thread_flag(TIF_FOREIGN_FPSTATE)) { - unsigned long tmp; - unsigned long flags; - struct fpsimd_state *st = ¤t->thread.fpsimd_state; task_fpsimd_load(current); this_cpu_write(fpsimd_last_state, st); st->cpu = smp_processor_id(); - - if (IS_ENABLED(CONFIG_ARM64_SVE)) { - /* - * Flip SVE enable for userspace if it doesn't - * match the current_task. - */ - asm ("mrs %0, cpacr_el1" : "=r" (tmp)); - flags = current_thread_info()->flags; - if ((tmp ^ (unsigned long)flags) & (1 << 17)) { - tmp ^= 1 << 17; - asm volatile ("msr cpacr_el1, %0" :: "r" (tmp)); - } - } } preempt_enable(); }