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Fri, 31 Mar 2017 09:04:33 +0000 (GMT) X-AuditID: b6c32a35-f79806d000002bf4-bc-58de1ba1b5dd Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1new.samsung.com (EPCPMTA) with SMTP id EF.E8.05715.1AB1ED85; Fri, 31 Mar 2017 18:04:33 +0900 (KST) Received: from smitha-fedora.sisodomain.com ([107.108.83.49]) by mmp2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0ONO0041F976Z3C0@mmp2.samsung.com>; Fri, 31 Mar 2017 18:04:33 +0900 (KST) From: Smitha T Murthy To: linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [Patch v3 03/11] [media] s5p-mfc: Use min scratch buffer size as provided by F/W Date: Fri, 31 Mar 2017 14:36:32 +0530 Message-id: <1490951200-32070-4-git-send-email-smitha.t@samsung.com> X-Mailer: git-send-email 1.7.2.3 In-reply-to: <1490951200-32070-1-git-send-email-smitha.t@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrBIsWRmVeSWpSXmKPExsWy7bCmnu4i6XsRBju8LW6tO8dqcWTtVSaL mSfaWS3On9/AbnG26Q27xabH11gtLu+aw2bRs2Erq8XaI3fZLZZt+sNksWjrF3aLw2+Aiu/u 2cbowOuxaVUnm8fmJfUefVtWMXp83iTnceVII3sAaxSXTUpqTmZZapG+XQJXxp2TmxkLZgZV TJ5T3sB4xLWLkZNDQsBEomnOVxYIW0ziwr31bF2MXBxCAjsYJfpa57NAOO1MEn9u3GCC6Wi/ cYYRIjGHUeJa83dWCOc/o0TDyYvMIFVsAjoS396fZgOxRQRSJV6tWwtWxCzwg1Hi1rcbYAuF BaIlbvy7xApiswioSlz5+IMRxOYVcJG4OO8BK8Q6BYlXN9ayg9icAq4Sr78tBDtQQmAeu8TN 9feAEhxAjqzEpgPMEPUuErvXnYSyhSVeHd/CDmFLS6z6d4sJoreZUWLutmaorycwSqxsLYWw 7SUOXJkDFmcW4JN497WHFWI+r0RHmxBEiYfE1qN3oW5zlLh56BgzxPczGCU+/5nONIFRZgEj wypGsdSC4tz01GLDAkO94sTc4tK8dL3k/NxNjOD41zLdwTjlnM8hRgEORiUe3h2CdyOEWBPL iitzDzFKcDArifAuYbkXIcSbklhZlVqUH19UmpNafIhRmoNFSZxXdP21CCGB9MSS1OzU1ILU IpgsEwenFDBid6eKrz7Nf5/ZeGtY8qXZnv1yVy+7nY3VVbx5T9BeuZRBcu7qPSlnM2N7N/xj TLBxdnsl7DTjOcOt9Kkh0yY+Exd+/XiZ6qxA2XtbnU9EzjwV0p92hUnfTGL58qRNHf6RB2fI nlo21+n61x6X/w/+B1f1BUq2F+T4OUns/q+x7GF5ygaprxVKLMUZiYZazEXFiQClEiH++wIA AA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupikeLIzCtJLcpLzFFi42I5/e+xoO5C6XsRBscuqVrcWneO1eLI2qtM FjNPtLNanD+/gd3ibNMbdotNj6+xWlzeNYfNomfDVlaLtUfuslss2/SHyWLR1i/sFoffABXf 3bON0YHXY9OqTjaPzUvqPfq2rGL0+LxJzuPKkUb2ANYoN5uM1MSU1CKF1Lzk/JTMvHRbpdAQ N10LJYW8xNxUW6UIXd+QICWFssScUiDPyAANODgHuAcr6dsluGXcObmZsWBmUMXkOeUNjEdc uxg5OSQETCTab5xhhLDFJC7cW8/WxcjFISQwi1Fix/SnjBBOI5PEu/fL2UCq2AR0JL69Pw1m iwikSqzdep4VpIhZ4AejRNOBl+wgCWGBaIkb/y6xgtgsAqoSVz7+AFvBK+AicXHeA1aIdQoS r26sBavnFHCVeP1tIdhQIaCaV++XMk5g5F3AyLCKUSK1ILmgOCk91zAvtVyvODG3uDQvXS85 P3cTIzgenkntYDy4y/0QowAHoxIP7w7BuxFCrIllxZW5hxglOJiVRHiXsNyLEOJNSaysSi3K jy8qzUktPsRoCnTYRGYp0eR8YKzmlcQbmpibmBsbWJhbWpoYKYnzNs5+Fi4kkJ5YkpqdmlqQ WgTTx8TBKdXA2B/j94DlzWaeipXNdj9fFQcfWrhbjXvZzbNZV3d37GVn4TiS1tx1te3kk1k3 Fsx+z61rL+q66fEtYZXcQ0fav0W8WTXtQ1a58Ja0Vza3pysEOMySKC1b+qC5x2TPFdfP/ad0 v7BxNa1U3yb/cMu5Ak4tTRb7tVPeft2/iv+mZFZUi/o8ybjjr5VYijMSDbWYi4oTAQa4y5Wd AgAA X-MTR: 20000000000000000@CPGS X-CMS-MailID: 20170331090433epcas1p4491ae8b6539e065ee3320aff08373ace X-Msg-Generator: CA X-Sender-IP: 203.254.230.26 X-Local-Sender: =?UTF-8?B?U21pdGhhIFQgTXVydGh5G1NTSVItVHVybiBLZXkgU29sdXRp?= =?UTF-8?B?b25zG+yCvOyEseyghOyekBtMZWFkIEVuZ2luZWVy?= X-Global-Sender: =?UTF-8?B?U21pdGhhIFQgTXVydGh5G1NTSVItVHVybiBLZXkgU29sdXRp?= =?UTF-8?B?b25zG1NhbXN1bmcgRWxlY3Ryb25pY3MbTGVhZCBFbmdpbmVlcg==?= X-Sender-Code: =?UTF-8?B?QzEwG1NXQUhRG0MxMElEMDdJRDAxMDk5Nw==?= CMS-TYPE: 101P X-CMS-RootMailID: 20170331090433epcas1p4491ae8b6539e065ee3320aff08373ace X-RootMTR: 20170331090433epcas1p4491ae8b6539e065ee3320aff08373ace References: <1490951200-32070-1-git-send-email-smitha.t@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170331_020453_511025_51D2B88D X-CRM114-Status: GOOD ( 14.97 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: a.hajda@samsung.com, pankaj.dubey@samsung.com, kamil@wypas.org, krzk@kernel.org, jtp.park@samsung.com, kyungmin.park@samsung.com, s.nawrocki@samsung.com, Smitha T Murthy , mchehab@kernel.org, m.szyprowski@samsung.com MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP After MFC v8.0, mfc f/w lets the driver know how much scratch buffer size is required for decoder. If mfc f/w has the functionality, E_MIN_SCRATCH_BUFFER_SIZE, driver can know how much scratch buffer size is required for encoder too. Signed-off-by: Smitha T Murthy Reviewed-by: Andrzej Hajda --- drivers/media/platform/s5p-mfc/regs-mfc-v8.h | 2 + drivers/media/platform/s5p-mfc/s5p_mfc.c | 2 + drivers/media/platform/s5p-mfc/s5p_mfc_common.h | 1 + drivers/media/platform/s5p-mfc/s5p_mfc_enc.c | 5 ++ drivers/media/platform/s5p-mfc/s5p_mfc_opr.h | 4 ++ drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c | 68 ++++++++++++++++++------- 6 files changed, 65 insertions(+), 17 deletions(-) diff --git a/drivers/media/platform/s5p-mfc/regs-mfc-v8.h b/drivers/media/platform/s5p-mfc/regs-mfc-v8.h index 4d1c375..2cd396b 100644 --- a/drivers/media/platform/s5p-mfc/regs-mfc-v8.h +++ b/drivers/media/platform/s5p-mfc/regs-mfc-v8.h @@ -17,6 +17,7 @@ /* Additional registers for v8 */ #define S5P_FIMV_D_MVC_NUM_VIEWS_V8 0xf104 +#define S5P_FIMV_D_MIN_SCRATCH_BUFFER_SIZE_V8 0xf108 #define S5P_FIMV_D_FIRST_PLANE_DPB_SIZE_V8 0xf144 #define S5P_FIMV_D_SECOND_PLANE_DPB_SIZE_V8 0xf148 #define S5P_FIMV_D_MV_BUFFER_SIZE_V8 0xf150 @@ -84,6 +85,7 @@ #define S5P_FIMV_E_VBV_BUFFER_SIZE_V8 0xf78c #define S5P_FIMV_E_VBV_INIT_DELAY_V8 0xf790 +#define S5P_FIMV_E_MIN_SCRATCH_BUFFER_SIZE_V8 0xf894 #define S5P_FIMV_E_ASPECT_RATIO_V8 0xfb4c #define S5P_FIMV_E_EXTENDED_SAR_V8 0xfb50 diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc.c b/drivers/media/platform/s5p-mfc/s5p_mfc.c index 443ff7e..399c547 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc.c +++ b/drivers/media/platform/s5p-mfc/s5p_mfc.c @@ -520,6 +520,8 @@ static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx *ctx, dev); ctx->mv_count = s5p_mfc_hw_call(dev->mfc_ops, get_mv_count, dev); + ctx->scratch_buf_size = s5p_mfc_hw_call(dev->mfc_ops, + get_min_scratch_buf_size, dev); if (ctx->img_width == 0 || ctx->img_height == 0) ctx->state = MFCINST_ERROR; else diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_common.h b/drivers/media/platform/s5p-mfc/s5p_mfc_common.h index 3a4ca55..8368d5c2 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc_common.h +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_common.h @@ -724,6 +724,7 @@ void s5p_mfc_cleanup_queue(struct list_head *lh, struct vb2_queue *vq); #define IS_MFCV7_PLUS(dev) (dev->variant->version >= 0x70 ? 1 : 0) #define IS_MFCV8_PLUS(dev) (dev->variant->version >= 0x80 ? 1 : 0) #define IS_MFCV10(dev) (dev->variant->version >= 0xA0 ? 1 : 0) +#define FW_HAS_E_MIN_SCRATCH_BUF(dev) (IS_MFCV10(dev)) #define MFC_V5_BIT BIT(0) #define MFC_V6_BIT BIT(1) diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c b/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c index e81b359..57a40c0 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c @@ -813,6 +813,11 @@ static int enc_post_seq_start(struct s5p_mfc_ctx *ctx) get_enc_dpb_count, dev); if (ctx->pb_count < enc_pb_count) ctx->pb_count = enc_pb_count; + if (FW_HAS_E_MIN_SCRATCH_BUF(dev)) { + ctx->scratch_buf_size = s5p_mfc_hw_call(dev->mfc_ops, + get_e_min_scratch_buf_size, dev); + ctx->bank1.size += ctx->scratch_buf_size; + } ctx->state = MFCINST_HEAD_PRODUCED; } diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr.h b/drivers/media/platform/s5p-mfc/s5p_mfc_opr.h index b6ac417..6478f70 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr.h +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr.h @@ -169,6 +169,7 @@ struct s5p_mfc_regs { void __iomem *d_decoded_third_addr;/* only v7 */ void __iomem *d_used_dpb_flag_upper;/* v7 and v8 */ void __iomem *d_used_dpb_flag_lower;/* v7 and v8 */ + void __iomem *d_min_scratch_buffer_size; /* v10 */ /* encoder registers */ void __iomem *e_frame_width; @@ -268,6 +269,7 @@ struct s5p_mfc_regs { void __iomem *e_vp8_hierarchical_qp_layer0;/* v7 and v8 */ void __iomem *e_vp8_hierarchical_qp_layer1;/* v7 and v8 */ void __iomem *e_vp8_hierarchical_qp_layer2;/* v7 and v8 */ + void __iomem *e_min_scratch_buffer_size; /* v10 */ }; struct s5p_mfc_hw_ops { @@ -311,6 +313,8 @@ struct s5p_mfc_hw_ops { unsigned int (*get_pic_type_bot)(struct s5p_mfc_ctx *ctx); unsigned int (*get_crop_info_h)(struct s5p_mfc_ctx *ctx); unsigned int (*get_crop_info_v)(struct s5p_mfc_ctx *ctx); + int (*get_min_scratch_buf_size)(struct s5p_mfc_dev *dev); + int (*get_e_min_scratch_buf_size)(struct s5p_mfc_dev *dev); }; void s5p_mfc_init_hw_ops(struct s5p_mfc_dev *dev); diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c index 9dc106e..5f0da0b 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c @@ -110,7 +110,9 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx) switch (ctx->codec_mode) { case S5P_MFC_CODEC_H264_DEC: case S5P_MFC_CODEC_H264_MVC_DEC: - if (IS_MFCV8_PLUS(dev)) + if (IS_MFCV10(dev)) + mfc_debug(2, "Use min scratch buffer size\n"); + else if (IS_MFCV8_PLUS(dev)) ctx->scratch_buf_size = S5P_FIMV_SCRATCH_BUF_SIZE_H264_DEC_V8( mb_width, @@ -127,7 +129,9 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx) (ctx->mv_count * ctx->mv_size); break; case S5P_MFC_CODEC_MPEG4_DEC: - if (IS_MFCV7_PLUS(dev)) { + if (IS_MFCV10(dev)) + mfc_debug(2, "Use min scratch buffer size\n"); + else if (IS_MFCV7_PLUS(dev)) { ctx->scratch_buf_size = S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_DEC_V7( mb_width, @@ -145,10 +149,14 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx) break; case S5P_MFC_CODEC_VC1RCV_DEC: case S5P_MFC_CODEC_VC1_DEC: - ctx->scratch_buf_size = - S5P_FIMV_SCRATCH_BUF_SIZE_VC1_DEC_V6( - mb_width, - mb_height); + if (IS_MFCV10(dev)) + mfc_debug(2, "Use min scratch buffer size\n"); + else + ctx->scratch_buf_size = + S5P_FIMV_SCRATCH_BUF_SIZE_VC1_DEC_V6( + mb_width, + mb_height); + ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6); ctx->bank1.size = ctx->scratch_buf_size; @@ -158,16 +166,21 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx) ctx->bank2.size = 0; break; case S5P_MFC_CODEC_H263_DEC: - ctx->scratch_buf_size = - S5P_FIMV_SCRATCH_BUF_SIZE_H263_DEC_V6( - mb_width, - mb_height); + if (IS_MFCV10(dev)) + mfc_debug(2, "Use min scratch buffer size\n"); + else + ctx->scratch_buf_size = + S5P_FIMV_SCRATCH_BUF_SIZE_H263_DEC_V6( + mb_width, + mb_height); ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6); ctx->bank1.size = ctx->scratch_buf_size; break; case S5P_MFC_CODEC_VP8_DEC: - if (IS_MFCV8_PLUS(dev)) + if (IS_MFCV10(dev)) + mfc_debug(2, "Use min scratch buffer size\n"); + else if (IS_MFCV8_PLUS(dev)) ctx->scratch_buf_size = S5P_FIMV_SCRATCH_BUF_SIZE_VP8_DEC_V8( mb_width, @@ -182,7 +195,9 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx) ctx->bank1.size = ctx->scratch_buf_size; break; case S5P_MFC_CODEC_H264_ENC: - if (IS_MFCV8_PLUS(dev)) + if (IS_MFCV10(dev)) { + mfc_debug(2, "Use min scratch buffer size\n"); + } else if (IS_MFCV8_PLUS(dev)) ctx->scratch_buf_size = S5P_FIMV_SCRATCH_BUF_SIZE_H264_ENC_V8( mb_width, @@ -202,10 +217,13 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx) break; case S5P_MFC_CODEC_MPEG4_ENC: case S5P_MFC_CODEC_H263_ENC: - ctx->scratch_buf_size = - S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_ENC_V6( - mb_width, - mb_height); + if (IS_MFCV10(dev)) { + mfc_debug(2, "Use min scratch buffer size\n"); + } else + ctx->scratch_buf_size = + S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_ENC_V6( + mb_width, + mb_height); ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6); ctx->bank1.size = @@ -215,7 +233,9 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx) ctx->bank2.size = 0; break; case S5P_MFC_CODEC_VP8_ENC: - if (IS_MFCV8_PLUS(dev)) + if (IS_MFCV10(dev)) { + mfc_debug(2, "Use min scratch buffer size\n"); + } else if (IS_MFCV8_PLUS(dev)) ctx->scratch_buf_size = S5P_FIMV_SCRATCH_BUF_SIZE_VP8_ENC_V8( mb_width, @@ -1902,6 +1922,16 @@ static int s5p_mfc_get_mv_count_v6(struct s5p_mfc_dev *dev) return readl(dev->mfc_regs->d_min_num_mv); } +static int s5p_mfc_get_min_scratch_buf_size(struct s5p_mfc_dev *dev) +{ + return readl(dev->mfc_regs->d_min_scratch_buffer_size); +} + +static int s5p_mfc_get_e_min_scratch_buf_size(struct s5p_mfc_dev *dev) +{ + return readl(dev->mfc_regs->e_min_scratch_buffer_size); +} + static int s5p_mfc_get_inst_no_v6(struct s5p_mfc_dev *dev) { return readl(dev->mfc_regs->ret_instance_id); @@ -2160,6 +2190,7 @@ const struct s5p_mfc_regs *s5p_mfc_init_regs_v6_plus(struct s5p_mfc_dev *dev) R(d_ret_picture_tag_bot, S5P_FIMV_D_RET_PICTURE_TAG_BOT_V8); R(d_display_crop_info1, S5P_FIMV_D_DISPLAY_CROP_INFO1_V8); R(d_display_crop_info2, S5P_FIMV_D_DISPLAY_CROP_INFO2_V8); + R(d_min_scratch_buffer_size, S5P_FIMV_D_MIN_SCRATCH_BUFFER_SIZE_V8); /* encoder registers */ R(e_padding_ctrl, S5P_FIMV_E_PADDING_CTRL_V8); @@ -2175,6 +2206,7 @@ const struct s5p_mfc_regs *s5p_mfc_init_regs_v6_plus(struct s5p_mfc_dev *dev) R(e_aspect_ratio, S5P_FIMV_E_ASPECT_RATIO_V8); R(e_extended_sar, S5P_FIMV_E_EXTENDED_SAR_V8); R(e_h264_options, S5P_FIMV_E_H264_OPTIONS_V8); + R(e_min_scratch_buffer_size, S5P_FIMV_E_MIN_SCRATCH_BUFFER_SIZE_V8); done: return &mfc_regs; @@ -2223,6 +2255,8 @@ static struct s5p_mfc_hw_ops s5p_mfc_ops_v6 = { .get_pic_type_bot = s5p_mfc_get_pic_type_bot_v6, .get_crop_info_h = s5p_mfc_get_crop_info_h_v6, .get_crop_info_v = s5p_mfc_get_crop_info_v_v6, + .get_min_scratch_buf_size = s5p_mfc_get_min_scratch_buf_size, + .get_e_min_scratch_buf_size = s5p_mfc_get_e_min_scratch_buf_size, }; struct s5p_mfc_hw_ops *s5p_mfc_init_hw_ops_v6(void)