| Message ID | 1491291403-29893-4-git-send-email-ganapatrao.kulkarni@cavium.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, Apr 04, 2017 at 01:06:43PM +0530, Ganapatrao Kulkarni wrote: > This is not a full event list, but a short list of useful events. > > Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com> > --- > tools/perf/pmu-events/arch/arm64/mapfile.csv | 2 + > .../arm64/thunderx2/implementation-defined.json | 72 ++++++++++++++++++++++ > 2 files changed, 74 insertions(+) > create mode 100644 tools/perf/pmu-events/arch/arm64/mapfile.csv > create mode 100644 tools/perf/pmu-events/arch/arm64/thunderx2/implementation-defined.json > > diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv > new file mode 100644 > index 0000000..ba30e43 > --- /dev/null > +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv > @@ -0,0 +1,2 @@ > +Family-model,Version,Filename,EventType > +0x00000000420f5161,v1,thunderx2,core > diff --git a/tools/perf/pmu-events/arch/arm64/thunderx2/implementation-defined.json b/tools/perf/pmu-events/arch/arm64/thunderx2/implementation-defined.json > new file mode 100644 > index 0000000..360e084 > --- /dev/null > +++ b/tools/perf/pmu-events/arch/arm64/thunderx2/implementation-defined.json > @@ -0,0 +1,72 @@ > +[ > + { > + "PublicDescription": "Attributable Level 1 data cache access, read", > + "EventCode": "0x40", > + "EventName": "l1d_cache_access_read", > + "BriefDescription": "l1d cache access, read", > + "CPU" :"armv8_pmuv3_0" Please let's not hard-code the name like this. Surely we can get rid of this? The kernel doesn't currently name PMUs as armv8_pmuv3_*, and as that can differ across DT/ACPI and in big.LITTLE, I don't think it makes sense to try to rely one particular string regardless. Thanks, Mark.
On Tue, Apr 4, 2017 at 5:58 PM, Mark Rutland <mark.rutland@arm.com> wrote: > On Tue, Apr 04, 2017 at 01:06:43PM +0530, Ganapatrao Kulkarni wrote: >> This is not a full event list, but a short list of useful events. >> >> Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com> >> --- >> tools/perf/pmu-events/arch/arm64/mapfile.csv | 2 + >> .../arm64/thunderx2/implementation-defined.json | 72 ++++++++++++++++++++++ >> 2 files changed, 74 insertions(+) >> create mode 100644 tools/perf/pmu-events/arch/arm64/mapfile.csv >> create mode 100644 tools/perf/pmu-events/arch/arm64/thunderx2/implementation-defined.json >> >> diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv >> new file mode 100644 >> index 0000000..ba30e43 >> --- /dev/null >> +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv >> @@ -0,0 +1,2 @@ >> +Family-model,Version,Filename,EventType >> +0x00000000420f5161,v1,thunderx2,core >> diff --git a/tools/perf/pmu-events/arch/arm64/thunderx2/implementation-defined.json b/tools/perf/pmu-events/arch/arm64/thunderx2/implementation-defined.json >> new file mode 100644 >> index 0000000..360e084 >> --- /dev/null >> +++ b/tools/perf/pmu-events/arch/arm64/thunderx2/implementation-defined.json >> @@ -0,0 +1,72 @@ >> +[ >> + { >> + "PublicDescription": "Attributable Level 1 data cache access, read", >> + "EventCode": "0x40", >> + "EventName": "l1d_cache_access_read", >> + "BriefDescription": "l1d cache access, read", >> + "CPU" :"armv8_pmuv3_0" > > Please let's not hard-code the name like this. Surely we can get rid of this? > > The kernel doesn't currently name PMUs as armv8_pmuv3_*, and as that can > differ across DT/ACPI and in big.LITTLE, I don't think it makes sense to > try to rely one particular string regardless. This string/name is fixed for a platform. having name here is essential to know which devices among pmu (armv8_pmuv3_0, breakpoint, software) devices, these jevents to be added. also this json file is specific to a arch/soc/board, it is not a generic file to be common. > > Thanks, > Mark. thanks Ganapat
On Wed, Apr 05, 2017 at 02:42:39PM +0530, Ganapatrao Kulkarni wrote: > On Tue, Apr 4, 2017 at 5:58 PM, Mark Rutland <mark.rutland@arm.com> wrote: > > On Tue, Apr 04, 2017 at 01:06:43PM +0530, Ganapatrao Kulkarni wrote: > >> This is not a full event list, but a short list of useful events. > >> > >> Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com> > >> --- > >> tools/perf/pmu-events/arch/arm64/mapfile.csv | 2 + > >> .../arm64/thunderx2/implementation-defined.json | 72 ++++++++++++++++++++++ > >> 2 files changed, 74 insertions(+) > >> create mode 100644 tools/perf/pmu-events/arch/arm64/mapfile.csv > >> create mode 100644 tools/perf/pmu-events/arch/arm64/thunderx2/implementation-defined.json > >> > >> diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv > >> new file mode 100644 > >> index 0000000..ba30e43 > >> --- /dev/null > >> +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv > >> @@ -0,0 +1,2 @@ > >> +Family-model,Version,Filename,EventType > >> +0x00000000420f5161,v1,thunderx2,core > >> diff --git a/tools/perf/pmu-events/arch/arm64/thunderx2/implementation-defined.json b/tools/perf/pmu-events/arch/arm64/thunderx2/implementation-defined.json > >> new file mode 100644 > >> index 0000000..360e084 > >> --- /dev/null > >> +++ b/tools/perf/pmu-events/arch/arm64/thunderx2/implementation-defined.json > >> @@ -0,0 +1,72 @@ > >> +[ > >> + { > >> + "PublicDescription": "Attributable Level 1 data cache access, read", > >> + "EventCode": "0x40", > >> + "EventName": "l1d_cache_access_read", > >> + "BriefDescription": "l1d cache access, read", > >> + "CPU" :"armv8_pmuv3_0" > > > > Please let's not hard-code the name like this. Surely we can get rid of this? > > > > The kernel doesn't currently name PMUs as armv8_pmuv3_*, and as that can > > differ across DT/ACPI and in big.LITTLE, I don't think it makes sense to > > try to rely one particular string regardless. > > This string/name is fixed for a platform. having name here is essential to > know which devices among pmu (armv8_pmuv3_0, breakpoint, software) > devices, these jevents to be added. > also this json file is specific to a arch/soc/board, it is not a > generic file to be common. This file describe the events of a CPU PMU, and CPUs are not specific to a platform in general. There are many systems using Cortex-A57, for example. Across big.LITTLE SoCs with Cortex-A57, there's no guarantee as to whether the Cortex-A57 cores would be named armv8_pmuv3_0, or armv8_pmuv3_1, etc. This would depend on the boot CPU, probe order of secondaries, etc. I appreciate that your platform is homnogeneous, and you may not expect the core to be reused in any heterogeneous system. However, I think that if we're going to make this work for arm64 we should handle the general case, rather than only having it support a limited set of platforms. Currently, we don't have an "official" way of identifying which PMUs are CPU PMUs, but one way we could idtentify them would be to look at if they have a "cpus" attribute under sysfs (rather than a "cpumask" attribute). Thanks, Mark.
On Wed, Apr 5, 2017 at 3:35 PM, Mark Rutland <mark.rutland@arm.com> wrote: > On Wed, Apr 05, 2017 at 02:42:39PM +0530, Ganapatrao Kulkarni wrote: >> On Tue, Apr 4, 2017 at 5:58 PM, Mark Rutland <mark.rutland@arm.com> wrote: >> > On Tue, Apr 04, 2017 at 01:06:43PM +0530, Ganapatrao Kulkarni wrote: >> >> This is not a full event list, but a short list of useful events. >> >> >> >> Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com> >> >> --- >> >> tools/perf/pmu-events/arch/arm64/mapfile.csv | 2 + >> >> .../arm64/thunderx2/implementation-defined.json | 72 ++++++++++++++++++++++ >> >> 2 files changed, 74 insertions(+) >> >> create mode 100644 tools/perf/pmu-events/arch/arm64/mapfile.csv >> >> create mode 100644 tools/perf/pmu-events/arch/arm64/thunderx2/implementation-defined.json >> >> >> >> diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv >> >> new file mode 100644 >> >> index 0000000..ba30e43 >> >> --- /dev/null >> >> +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv >> >> @@ -0,0 +1,2 @@ >> >> +Family-model,Version,Filename,EventType >> >> +0x00000000420f5161,v1,thunderx2,core >> >> diff --git a/tools/perf/pmu-events/arch/arm64/thunderx2/implementation-defined.json b/tools/perf/pmu-events/arch/arm64/thunderx2/implementation-defined.json >> >> new file mode 100644 >> >> index 0000000..360e084 >> >> --- /dev/null >> >> +++ b/tools/perf/pmu-events/arch/arm64/thunderx2/implementation-defined.json >> >> @@ -0,0 +1,72 @@ >> >> +[ >> >> + { >> >> + "PublicDescription": "Attributable Level 1 data cache access, read", >> >> + "EventCode": "0x40", >> >> + "EventName": "l1d_cache_access_read", >> >> + "BriefDescription": "l1d cache access, read", >> >> + "CPU" :"armv8_pmuv3_0" >> > >> > Please let's not hard-code the name like this. Surely we can get rid of this? >> > >> > The kernel doesn't currently name PMUs as armv8_pmuv3_*, and as that can >> > differ across DT/ACPI and in big.LITTLE, I don't think it makes sense to >> > try to rely one particular string regardless. >> >> This string/name is fixed for a platform. having name here is essential to >> know which devices among pmu (armv8_pmuv3_0, breakpoint, software) >> devices, these jevents to be added. >> also this json file is specific to a arch/soc/board, it is not a >> generic file to be common. > > This file describe the events of a CPU PMU, and CPUs are not specific to > a platform in general. There are many systems using Cortex-A57, for > example. > > Across big.LITTLE SoCs with Cortex-A57, there's no guarantee as to > whether the Cortex-A57 cores would be named armv8_pmuv3_0, or > armv8_pmuv3_1, etc. This would depend on the boot CPU, probe order of > secondaries, etc. OK, we may not have complete name however, common part can be used to recognize the PMU CORE devices from /sys/bus/event_source/devices i.e we can have CPU id as "armv8_pmuv3". same is extended to UNCORE as well. mapfile.csv file will have entry for both BIG and LITTLE processors event files. the jevents creates table of pmu_events_map for all entries present in mapfile.csv file while lookup, which ever pmu matches the cpuid of pmu_events_map then corresponding table created from json file is used to add the jevents to that PMU. > > I appreciate that your platform is homnogeneous, and you may not expect > the core to be reused in any heterogeneous system. However, I think that > if we're going to make this work for arm64 we should handle the general > case, rather than only having it support a limited set of platforms. > > Currently, we don't have an "official" way of identifying which PMUs are > CPU PMUs, but one way we could idtentify them would be to look at if > they have a "cpus" attribute under sysfs (rather than a "cpumask" > attribute). > > Thanks, > Mark. thanks Ganapat
On Thu, Apr 06, 2017 at 09:50:33AM +0530, Ganapatrao Kulkarni wrote: > On Wed, Apr 5, 2017 at 3:35 PM, Mark Rutland <mark.rutland@arm.com> wrote: > > On Wed, Apr 05, 2017 at 02:42:39PM +0530, Ganapatrao Kulkarni wrote: > >> On Tue, Apr 4, 2017 at 5:58 PM, Mark Rutland <mark.rutland@arm.com> wrote: > >> > On Tue, Apr 04, 2017 at 01:06:43PM +0530, Ganapatrao Kulkarni wrote: > >> >> + "CPU" :"armv8_pmuv3_0" > >> > > >> > Please let's not hard-code the name like this. Surely we can get rid of this? > >> > > >> > The kernel doesn't currently name PMUs as armv8_pmuv3_*, and as that can > >> > differ across DT/ACPI and in big.LITTLE, I don't think it makes sense to > >> > try to rely one particular string regardless. > >> > >> This string/name is fixed for a platform. having name here is essential to > >> know which devices among pmu (armv8_pmuv3_0, breakpoint, software) > >> devices, these jevents to be added. > >> also this json file is specific to a arch/soc/board, it is not a > >> generic file to be common. > > > > This file describe the events of a CPU PMU, and CPUs are not specific to > > a platform in general. There are many systems using Cortex-A57, for > > example. > > > > Across big.LITTLE SoCs with Cortex-A57, there's no guarantee as to > > whether the Cortex-A57 cores would be named armv8_pmuv3_0, or > > armv8_pmuv3_1, etc. This would depend on the boot CPU, probe order of > > secondaries, etc. > > OK, we may not have complete name however, common part can be used to recognize > the PMU CORE devices from /sys/bus/event_source/devices > i.e we can have CPU id as "armv8_pmuv3". For better or worse, that's not the case on DT systems. I'd much rather that we identified the CPU PMUs without requiring particular names (e.g by looking for a "cpus" attribute). > same is extended to UNCORE as well. Could you elaborate on that? I'm not sure I follow. > mapfile.csv file will have entry for both BIG and LITTLE processors event files. > the jevents creates table of pmu_events_map for all entries present in > mapfile.csv file > while lookup, which ever pmu matches the cpuid of pmu_events_map > then corresponding table created from json file is used to add the > jevents to that PMU. Sorry, but I don't follow how that's related to the above. Thanks, Mark.
Hi Mark, On Thu, Apr 6, 2017 at 3:25 PM, Mark Rutland <mark.rutland@arm.com> wrote: > On Thu, Apr 06, 2017 at 09:50:33AM +0530, Ganapatrao Kulkarni wrote: >> On Wed, Apr 5, 2017 at 3:35 PM, Mark Rutland <mark.rutland@arm.com> wrote: >> > On Wed, Apr 05, 2017 at 02:42:39PM +0530, Ganapatrao Kulkarni wrote: >> >> On Tue, Apr 4, 2017 at 5:58 PM, Mark Rutland <mark.rutland@arm.com> wrote: >> >> > On Tue, Apr 04, 2017 at 01:06:43PM +0530, Ganapatrao Kulkarni wrote: > >> >> >> + "CPU" :"armv8_pmuv3_0" >> >> > >> >> > Please let's not hard-code the name like this. Surely we can get rid of this? >> >> > >> >> > The kernel doesn't currently name PMUs as armv8_pmuv3_*, and as that can >> >> > differ across DT/ACPI and in big.LITTLE, I don't think it makes sense to >> >> > try to rely one particular string regardless. >> >> >> >> This string/name is fixed for a platform. having name here is essential to >> >> know which devices among pmu (armv8_pmuv3_0, breakpoint, software) >> >> devices, these jevents to be added. >> >> also this json file is specific to a arch/soc/board, it is not a >> >> generic file to be common. >> > >> > This file describe the events of a CPU PMU, and CPUs are not specific to >> > a platform in general. There are many systems using Cortex-A57, for >> > example. >> > >> > Across big.LITTLE SoCs with Cortex-A57, there's no guarantee as to >> > whether the Cortex-A57 cores would be named armv8_pmuv3_0, or >> > armv8_pmuv3_1, etc. This would depend on the boot CPU, probe order of >> > secondaries, etc. some of the applications(perf etc) use sysfs files of perf PMU CORE devices. at present the names are created as per SOC/platform like armv8_pmuv3, armv8_cavium_thunder, armv8_cortex_a57 etc. cpu_pmu->name = "armv8_cavium_thunder"; can we please have common name similar to x86(cpu) and call them as cpu_0 and cpu_1? >> >> OK, we may not have complete name however, common part can be used to recognize >> the PMU CORE devices from /sys/bus/event_source/devices >> i.e we can have CPU id as "armv8_pmuv3". > > For better or worse, that's not the case on DT systems. > > I'd much rather that we identified the CPU PMUs without requiring > particular names (e.g by looking for a "cpus" attribute). > >> same is extended to UNCORE as well. > > Could you elaborate on that? I'm not sure I follow. > >> mapfile.csv file will have entry for both BIG and LITTLE processors event files. >> the jevents creates table of pmu_events_map for all entries present in >> mapfile.csv file >> while lookup, which ever pmu matches the cpuid of pmu_events_map >> then corresponding table created from json file is used to add the >> jevents to that PMU. > > Sorry, but I don't follow how that's related to the above. > > Thanks, > Mark. thanks Ganapat
On Wed, Apr 19, 2017 at 11:37:31PM +0530, Ganapatrao Kulkarni wrote: > Hi Mark, Hi, > On Thu, Apr 6, 2017 at 3:25 PM, Mark Rutland <mark.rutland@arm.com> wrote: > > On Thu, Apr 06, 2017 at 09:50:33AM +0530, Ganapatrao Kulkarni wrote: > >> On Wed, Apr 5, 2017 at 3:35 PM, Mark Rutland <mark.rutland@arm.com> wrote: > >> > On Wed, Apr 05, 2017 at 02:42:39PM +0530, Ganapatrao Kulkarni wrote: > >> >> On Tue, Apr 4, 2017 at 5:58 PM, Mark Rutland <mark.rutland@arm.com> wrote: > >> >> > On Tue, Apr 04, 2017 at 01:06:43PM +0530, Ganapatrao Kulkarni wrote: > > > >> >> >> + "CPU" :"armv8_pmuv3_0" > >> >> > > >> >> > Please let's not hard-code the name like this. Surely we can get rid of this? > >> >> > > >> >> > The kernel doesn't currently name PMUs as armv8_pmuv3_*, and as that can > >> >> > differ across DT/ACPI and in big.LITTLE, I don't think it makes sense to > >> >> > try to rely one particular string regardless. > >> >> > >> >> This string/name is fixed for a platform. having name here is essential to > >> >> know which devices among pmu (armv8_pmuv3_0, breakpoint, software) > >> >> devices, these jevents to be added. > >> >> also this json file is specific to a arch/soc/board, it is not a > >> >> generic file to be common. > >> > > >> > This file describe the events of a CPU PMU, and CPUs are not specific to > >> > a platform in general. There are many systems using Cortex-A57, for > >> > example. > >> > > >> > Across big.LITTLE SoCs with Cortex-A57, there's no guarantee as to > >> > whether the Cortex-A57 cores would be named armv8_pmuv3_0, or > >> > armv8_pmuv3_1, etc. This would depend on the boot CPU, probe order of > >> > secondaries, etc. > > some of the applications(perf etc) use sysfs files of perf PMU CORE devices. > at present the names are created as per SOC/platform like > armv8_pmuv3, armv8_cavium_thunder, armv8_cortex_a57 etc. > > cpu_pmu->name = "armv8_cavium_thunder"; > > can we please have common name similar to x86(cpu) and call them as > cpu_0 and cpu_1? I don't see how that helps in this case? I'd rather that we expose some mechanism to determine whether a PMU is a CPU PMU, other than the name. Userspace can then throw away the name if it so wishes, and it doesn't have the potential to break existing users. Thanks, Mark.
diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv new file mode 100644 index 0000000..ba30e43 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv @@ -0,0 +1,2 @@ +Family-model,Version,Filename,EventType +0x00000000420f5161,v1,thunderx2,core diff --git a/tools/perf/pmu-events/arch/arm64/thunderx2/implementation-defined.json b/tools/perf/pmu-events/arch/arm64/thunderx2/implementation-defined.json new file mode 100644 index 0000000..360e084 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/thunderx2/implementation-defined.json @@ -0,0 +1,72 @@ +[ + { + "PublicDescription": "Attributable Level 1 data cache access, read", + "EventCode": "0x40", + "EventName": "l1d_cache_access_read", + "BriefDescription": "l1d cache access, read", + "CPU" :"armv8_pmuv3_0" + }, + { + "PublicDescription": "Attributable Level 1 data cache access, write ", + "EventCode": "0x41", + "EventName": "l1d_cache_access_write", + "BriefDescription": "l1d cache access, write", + "CPU" :"armv8_pmuv3_0" + }, + { + "PublicDescription": "Attributable Level 1 data cache refill, read", + "EventCode": "0x42", + "EventName": "l1d_cache_refill_read", + "BriefDescription": "l1d cache refill, read", + "CPU" :"armv8_pmuv3_0" + }, + { + "PublicDescription": "Attributable Level 1 data cache refill, write", + "EventCode": "0x43", + "EventName": "l1d_cache_refill_write", + "BriefDescription": "l1d refill, write", + "CPU" :"armv8_pmuv3_0" + }, + { + "PublicDescription": "Attributable Level 1 data TLB refill, read", + "EventCode": "0x4C", + "EventName": "l1d_tlb_refill_read", + "BriefDescription": "l1d tlb refill, read", + "CPU" :"armv8_pmuv3_0" + }, + { + "PublicDescription": "Attributable Level 1 data TLB refill, write", + "EventCode": "0x4D", + "EventName": "l1d_tlb_refill_write", + "BriefDescription": "l1d tlb refill, write", + "CPU" :"armv8_pmuv3_0" + }, + { + "PublicDescription": "Attributable Level 1 data or unified TLB access, read", + "EventCode": "0x4E", + "EventName": "l1d_tlb_read", + "BriefDescription": "l1d tlb, read", + "CPU" :"armv8_pmuv3_0" + }, + { + "PublicDescription": "Attributable Level 1 data or unified TLB access, write", + "EventCode": "0x4F", + "EventName": "l1d_tlb_write", + "BriefDescription": "l1d tlb, write", + "CPU" :"armv8_pmuv3_0" + }, + { + "PublicDescription": "Bus access, read", + "EventCode": "0x60", + "EventName": "bus_access_read", + "BriefDescription": "Bus access, read", + "CPU" :"armv8_pmuv3_0" + }, + { + "PublicDescription": "Bus access, write", + "EventCode": "0x61", + "EventName": "bus_access_write", + "BriefDescription": "Bus access, write", + "CPU" :"armv8_pmuv3_0" + } +]
This is not a full event list, but a short list of useful events. Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com> --- tools/perf/pmu-events/arch/arm64/mapfile.csv | 2 + .../arm64/thunderx2/implementation-defined.json | 72 ++++++++++++++++++++++ 2 files changed, 74 insertions(+) create mode 100644 tools/perf/pmu-events/arch/arm64/mapfile.csv create mode 100644 tools/perf/pmu-events/arch/arm64/thunderx2/implementation-defined.json