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Mon, 22 May 2017 07:02:11 +0000 From: Jayachandran C To: Catalin Marinas , Will Deacon , linux-arm-kernel@lists.infradead.org Subject: [PATCH 2/2] arm64: switch ioremap_wc to use Device GRE Date: Mon, 22 May 2017 07:01:47 +0000 Message-Id: <1495436507-81890-3-git-send-email-jnair@caviumnetworks.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1495436507-81890-1-git-send-email-jnair@caviumnetworks.com> References: <1495436507-81890-1-git-send-email-jnair@caviumnetworks.com> MIME-Version: 1.0 X-Originating-IP: [50.233.148.156] X-ClientProxiedBy: CY4PR13CA0032.namprd13.prod.outlook.com (10.173.156.146) To BN6PR07MB2993.namprd07.prod.outlook.com (10.172.106.11) X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN6PR07MB2993: X-MS-Office365-Filtering-Correlation-Id: 48aac45d-3b0a-44f4-0843-08d4a0e078ce X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(22001)(201703131423075)(201703031133081); SRVR:BN6PR07MB2993; X-Microsoft-Exchange-Diagnostics: 1; BN6PR07MB2993; 3:vGO2xmMgF46bEPbAVOiZR5Jxsnid/tncFPOxSKx3PiwuhbbiPOTNzcVf4Den/vGQTKbLD6sSm6muzdLTsfzrFSpDtZ70hgZqsYrxF4A0tT7VCKE5qM/SysmYCzYYfuJfFd/3Hp2/GRkjQtOhlRYFkO+/hHFSim4am3stWS1B48Qbd5nHZ3JLBjKoc7Ihzt3wj1sO2oen5kSBWkQyzuIqOgzpUmQXhYhisgLlRzypSqV4xdHPetT1rEOWxMAGOIrgTm7H0LANOI9oVQEwL5peXHwB3tXtVKWgdlrMqCmt8jppe/mxEIjjmJ/ER/cUkOJjmvtZfeHa2FFi8prHwzUWRw==; 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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Robert Richter , Jayachandran C , Alexander Graf Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The device "Gather" attribute is defined in the ARMv8 ARM as: "The Gathering attribute determines whether it is permissible for either: * Multiple memory accesses of the same type, read or write, to the same memory location to be merged into a single transaction. * Multiple memory accesses of the same type, read or write, to different memory locations to be merged into a single memory transaction on an interconnect." This attribute is more appropriate for the write combining ioremap_wc() than the non-cached memory attribute used now, so update the ioremap_wc implementation to use it. Signed-off-by: Jayachandran C --- arch/arm64/include/asm/io.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/io.h b/arch/arm64/include/asm/io.h index 35b2e50..b1c92e3 100644 --- a/arch/arm64/include/asm/io.h +++ b/arch/arm64/include/asm/io.h @@ -168,7 +168,7 @@ extern void __iomem *ioremap_cache(phys_addr_t phys_addr, size_t size); #define ioremap(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE)) #define ioremap_nocache(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE)) -#define ioremap_wc(addr, size) __ioremap((addr), (size), __pgprot(PROT_NORMAL_NC)) +#define ioremap_wc(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_GRE)) #define ioremap_wt(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE)) #define iounmap __iounmap