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Mon, 5 Jun 2017 06:51:42 +0000 From: Ganapatrao Kulkarni To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 1/2] perf: uncore: Adding documentation for ThunderX2 pmu uncore driver Date: Mon, 5 Jun 2017 12:21:03 +0530 Message-Id: <1496645464-26062-2-git-send-email-ganapatrao.kulkarni@cavium.com> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1496645464-26062-1-git-send-email-ganapatrao.kulkarni@cavium.com> References: <1496645464-26062-1-git-send-email-ganapatrao.kulkarni@cavium.com> MIME-Version: 1.0 X-Originating-IP: [111.93.218.67] X-ClientProxiedBy: PN1PR01CA0099.INDPRD01.PROD.OUTLOOK.COM (10.174.144.15) To CY1PR07MB2569.namprd07.prod.outlook.com (10.167.16.24) X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY1PR07MB2569: X-MS-Office365-Filtering-Correlation-Id: 773d1dd3-61cc-46c1-5123-08d4abdf5562 X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(22001)(201703131423075)(201703031133081); SRVR:CY1PR07MB2569; X-Microsoft-Exchange-Diagnostics: 1; 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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, alexander.shishkin@linux.intel.com, catalin.marinas@arm.com, Will.Deacon@arm.com, acme@kernel.org, peterz@infradead.org, mingo@redhat.com, jnair@caviumnetworks.com, gpkulkarni@gmail.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Documentation for the UNCORE PMUs on Cavium's ThunderX2 SoC. The SoC has PMU support in its L3 cache controller (L3C) and in the DDR4 Memory Controller (DMC). Signed-off-by: Ganapatrao Kulkarni --- Documentation/perf/thunderx2-pmu.txt | 60 ++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 Documentation/perf/thunderx2-pmu.txt diff --git a/Documentation/perf/thunderx2-pmu.txt b/Documentation/perf/thunderx2-pmu.txt new file mode 100644 index 0000000..eb8df9a --- /dev/null +++ b/Documentation/perf/thunderx2-pmu.txt @@ -0,0 +1,60 @@ + +Cavium ThunderX2 SoC Performance Monitoring Unit (PMU UNCORE) +============================================================= + +ThunderX2 SoC PMU consists of independent system wide PMUs such as +Level 3 Cache(L3C) and DDR4 Memory Controller(DMC). + +DMC: There are 8 independent PMUs to capture performance events corresponding +to 8 channels of DDR4 Memory Controller. Each PMU supports upto 4 counters. + +L3C: There are 16 independent PMUs to capture events corresponding to 16 tiles +of L3 cache. Each PMU supports up to 4 counters. + +PMU UNCORE (perf) driver +----------------------- + +The thunderx2-pmu driver registers several perf PMUs for DMC and L3C devices. +Each of the PMU provides description of its available events +and configuration options in sysfs. + see /sys/devices/uncore_