| Message ID | 1496654569-4749-1-git-send-email-hoeun.ryu@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Mon, Jun 05, 2017 at 06:22:20PM +0900, Hoeun Ryu wrote: > diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S > index 5e5720e..9ac2bec 100644 > --- a/arch/arm/mm/proc-v7-3level.S > +++ b/arch/arm/mm/proc-v7-3level.S > @@ -140,6 +140,7 @@ ENDPROC(cpu_v7_set_pte_ext) > * otherwise booting secondary CPUs would end up using TTBR1 for the > * identity mapping set up in TTBR0. > */ > + bichi \tmp, \tmp, #(1 << 16) @ clear TTBCR.T1SZ This looks insufficient. There's two bits here: * TTBR0/TTBR1 split (PAGE_OFFSET): * 0x40000000: T0SZ = 2, T1SZ = 0 (not used) * 0x80000000: T0SZ = 0, T1SZ = 1 * 0xc0000000: T0SZ = 0, T1SZ = 2 but you seem to only be clearing one bit.
On Mon, Jun 5, 2017 at 6:34 PM, Russell King - ARM Linux <linux@armlinux.org.uk> wrote: > On Mon, Jun 05, 2017 at 06:22:20PM +0900, Hoeun Ryu wrote: >> diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S >> index 5e5720e..9ac2bec 100644 >> --- a/arch/arm/mm/proc-v7-3level.S >> +++ b/arch/arm/mm/proc-v7-3level.S >> @@ -140,6 +140,7 @@ ENDPROC(cpu_v7_set_pte_ext) >> * otherwise booting secondary CPUs would end up using TTBR1 for the >> * identity mapping set up in TTBR0. >> */ >> + bichi \tmp, \tmp, #(1 << 16) @ clear TTBCR.T1SZ > > This looks insufficient. There's two bits here: > > * TTBR0/TTBR1 split (PAGE_OFFSET): > * 0x40000000: T0SZ = 2, T1SZ = 0 (not used) > * 0x80000000: T0SZ = 0, T1SZ = 1 > * 0xc0000000: T0SZ = 0, T1SZ = 2 > > but you seem to only be clearing one bit. Oh, I'm sorry for the mistake, I'll fix this like #(7 << 16) in v2. (There're 3 bits in TxSZ) Thank you for the review. > > -- > RMK's Patch system: http://www.armlinux.org.uk/developer/patches/ > FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up > according to speedtest.net.
diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S index 5e5720e..9ac2bec 100644 --- a/arch/arm/mm/proc-v7-3level.S +++ b/arch/arm/mm/proc-v7-3level.S @@ -140,6 +140,7 @@ ENDPROC(cpu_v7_set_pte_ext) * otherwise booting secondary CPUs would end up using TTBR1 for the * identity mapping set up in TTBR0. */ + bichi \tmp, \tmp, #(1 << 16) @ clear TTBCR.T1SZ orrls \tmp, \tmp, #TTBR1_SIZE @ TTBCR.T1SZ mcr p15, 0, \tmp, c2, c0, 2 @ TTBCR mov \tmp, \ttbr1, lsr #20
Clearing TTBCR.T1SZ explicitly when kernel runs on a configuration of PHYS_OFFSET > PAGE_OFFSET. Reading TTBCR in early boot stage might returns the value of the previous kernel's configuration, especially in case of kexec. For example, if normal kernel (first kernel) had run on a configuration of PHYS_OFFSET <= PAGE_OFFSET and crash kernel (second kernel) is running on a configuration PHYS_OFFSET > PAGE_OFFSET, which can happen because it depends on the reserved area for crash kernel, reading TTBCR and using the value without clearing TTBCR.T1SZ might risky because the value doesn't have a reset value for TTBCR.T1SZ. Signed-off-by: Hoeun Ryu <hoeun.ryu@gmail.com> --- arch/arm/mm/proc-v7-3level.S | 1 + 1 file changed, 1 insertion(+)