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bh=TboO9svFLLbSF7Z9DILQAbX2yWTGy5jU9NoE4U1OgcE=; b=anZT0NtWOZLRfj+E6WbTPqRc95EMCGl1NNUKpL2/PEmEpgaeur3YlUJsUo7l2b7Lb7 lFTqdSe2HozU3BIPdCjP+n25WYaQuVtGzlaH1+Qb9MFdxBkqsrKY/CsOxyK7LXhn110Y /67Alb/YN/gUP12xeutnvx/E+tYpzyvdyUuUjUhr/o93wpE+GexBQcPPfap64WtU5uej 1NB84GB8h0EtDpdaaSfSvF8mZ2i42ghCT8/eJt61zmaRutIXRiEDs7B7v4NWjm47EO0F l16BMJYRUnrfOPnlb9TaBFsV8CHIGWOvK9CdZ5/Iydek3nzq2bVVv7+4vOsafA1BXHCS dCaA== X-Gm-Message-State: AODbwcDf6fU0ByDC/PDAAwfSDxrmM9zED7/QcnzmXTba9PsGbIku2Bs7 0y63DCa3aAYcGA== X-Received: by 10.84.171.195 with SMTP id l61mr14014862plb.147.1496654848633; Mon, 05 Jun 2017 02:27:28 -0700 (PDT) Received: from sel-hryu-l2.corp.ad.wrs.com ([61.107.31.52]) by smtp.gmail.com with ESMTPSA id 187sm51396905pgc.46.2017.06.05.02.27.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Jun 2017 02:27:27 -0700 (PDT) From: Hoeun Ryu To: Russell King Subject: [PATCH] arm: LPAE: kexec: clear TTBCR.T1SZ explicitly when PHYS_OFFSET > PAGE_OFFSET Date: Mon, 5 Jun 2017 18:22:20 +0900 Message-Id: <1496654569-4749-1-git-send-email-hoeun.ryu@gmail.com> X-Mailer: git-send-email 2.7.4 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170605_022749_924001_0D48AB7D X-CRM114-Status: GOOD ( 11.61 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Hoeun Ryu , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Clearing TTBCR.T1SZ explicitly when kernel runs on a configuration of PHYS_OFFSET > PAGE_OFFSET. Reading TTBCR in early boot stage might returns the value of the previous kernel's configuration, especially in case of kexec. For example, if normal kernel (first kernel) had run on a configuration of PHYS_OFFSET <= PAGE_OFFSET and crash kernel (second kernel) is running on a configuration PHYS_OFFSET > PAGE_OFFSET, which can happen because it depends on the reserved area for crash kernel, reading TTBCR and using the value without clearing TTBCR.T1SZ might risky because the value doesn't have a reset value for TTBCR.T1SZ. Signed-off-by: Hoeun Ryu --- arch/arm/mm/proc-v7-3level.S | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S index 5e5720e..9ac2bec 100644 --- a/arch/arm/mm/proc-v7-3level.S +++ b/arch/arm/mm/proc-v7-3level.S @@ -140,6 +140,7 @@ ENDPROC(cpu_v7_set_pte_ext) * otherwise booting secondary CPUs would end up using TTBR1 for the * identity mapping set up in TTBR0. */ + bichi \tmp, \tmp, #(1 << 16) @ clear TTBCR.T1SZ orrls \tmp, \tmp, #TTBR1_SIZE @ TTBCR.T1SZ mcr p15, 0, \tmp, c2, c0, 2 @ TTBCR mov \tmp, \ttbr1, lsr #20