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bh=yChwpd+8XKYfMwYMSMkegJggV2qmZOvzWasGleenhLk=; b=S/lo20iMjqsAsHyjU5qC9uaRTQ1dA8ycX3UAc2J8AHBWyeyoprTg6Ou0ZsT4N3wCQo 6HFhW0Q/wYGYwLIN3kLFC7a/eB+eoMi8RyZ4n+vyzS1ZzhDuHFS17CZ0tmuInjR6fa/9 8UjFsn76PnIzQM3HYpjmmLd8PT/UlX8Ag/cyHHELBSM0zb3r7u/A0VVzO1MIU2Cjq6vy trevFtvg+VuTpmnhaKk1O3POBG0yggdk5Ws0IoTWAYSiPdH/9LKk6GPpERxUQ+9n73NV Y9w83A/aKDuUG5ycPVlGUcDEy6pju11z5vYyD41tQ3G3qdX6PyEx6p+8mK3XAqZ4dL+A mNEA== X-Gm-Message-State: AODbwcCKGzkoO29DB2t51BWOA9l3PTZm9OIIRHEsiqtDqwSe9N5EIlq2 hyun1kIlRSreMPUjYeg= X-Received: by 10.98.87.211 with SMTP id i80mr19773322pfj.231.1496657692554; Mon, 05 Jun 2017 03:14:52 -0700 (PDT) Received: from sel-hryu-l2.corp.ad.wrs.com ([61.107.31.52]) by smtp.gmail.com with ESMTPSA id a3sm53651222pfc.26.2017.06.05.03.14.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Jun 2017 03:14:51 -0700 (PDT) From: Hoeun Ryu To: Russell King Subject: [PATCHv2] arm: LPAE: kexec: clear TTBCR.T1SZ explicitly when PHYS_OFFSET > PAGE_OFFSET Date: Mon, 5 Jun 2017 19:06:26 +0900 Message-Id: <1496657199-29589-1-git-send-email-hoeun.ryu@gmail.com> X-Mailer: git-send-email 2.7.4 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170605_031513_512847_14FF798B X-CRM114-Status: GOOD ( 11.50 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Hoeun Ryu , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Clearing TTBCR.T1SZ explicitly when kernel runs on a configuration of PHYS_OFFSET > PAGE_OFFSET. Reading TTBCR in early boot stage might returns the value of the previous kernel's configuration, especially in case of kexec. For example, if normal kernel (first kernel) had run on a configuration of PHYS_OFFSET <= PAGE_OFFSET and crash kernel (second kernel) is running on a configuration PHYS_OFFSET > PAGE_OFFSET, which can happen because it depends on the reserved area for crash kernel, reading TTBCR and using the value without clearing TTBCR.T1SZ might risky because the value doesn't have a reset value for TTBCR.T1SZ. Signed-off-by: Hoeun Ryu --- arch/arm/mm/proc-v7-3level.S | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S index 5e5720e..81404b8 100644 --- a/arch/arm/mm/proc-v7-3level.S +++ b/arch/arm/mm/proc-v7-3level.S @@ -140,6 +140,7 @@ ENDPROC(cpu_v7_set_pte_ext) * otherwise booting secondary CPUs would end up using TTBR1 for the * identity mapping set up in TTBR0. */ + bichi \tmp, \tmp, #(7 << 16) @ clear TTBCR.T1SZ orrls \tmp, \tmp, #TTBR1_SIZE @ TTBCR.T1SZ mcr p15, 0, \tmp, c2, c0, 2 @ TTBCR mov \tmp, \ttbr1, lsr #20