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24:2MaIe1qd92Nux+9AFG3ljFo6trayMdyPgFMX03+XRhnvdUeuo0eg4zAoSlq9MfY8RHj+jAlFYCPDr6fulBE/oyastTlATSDq9XZv7vQMwnc= SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-Microsoft-Exchange-Diagnostics: 1; BY2PR03MB175; 7:hQ5WRFAYJ+pcxspiPwmuBZO2PFRWoVzz89uX8noXvhjUvJ02Xipspkraglu3xIkMjTSlFFdURlT1d3WhOcPwbqLKxFnPPrsM7Q/ST7lx9ti2t7b4Xd2nURIYjsQXwiKAM5qERH11W+irpy8FRWnSxylbpu70nFtkJfAQNWaPd7ayhriCA29hqd96VKQF3R3DvphP9UPi+L7UaY0i1bogLMUT2T0/nDRViLkYpXq1VB/xWULvfAqSApbHQnZdO81OfWZSb/rRDMehKiAB1N1p2w9WC4d0fza5C0WLNYIFwHchoJgM+ayeM9xh7YfsdO7uz9kKf9hFuIj7fjJcAWOYew== X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jun 2017 02:55:57.0984 (UTC) X-MS-Exchange-CrossTenant-Id: 5afe0b00-7697-4969-b663-5eab37d5f47e X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e; Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY2PR03MB175 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170612_195620_876756_F0F0061C X-CRM114-Status: GOOD ( 11.73 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: nikita.yoush@cogentembedded.com, Dong Aisheng , fugang.duan@nxp.com, dongas86@gmail.com, devicetree@vger.kernel.org, gregkh@linuxfoundation.org, yangbo.lu@nxp.com, linux-kernel@vger.kernel.org, stefan@agner.ch, andy.shevchenko@gmail.com, Mingkai.Hu@nxp.com, jslaby@suse.com, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The lpuart of imx7ulp is basically the same as ls1021a. It's also 32 bit width register, but unlike ls1021a, it's little endian. Besides that, imx7ulp lpuart has a minor different register layout from ls1021a. Cc: devicetree@vger.kernel.org Cc: Greg Kroah-Hartman Cc: Jiri Slaby Cc: Stefan Agner Cc: Mingkai Hu Cc: Yangbo Lu Acked-by: Rob Herring Acked-by: Fugang Duan Signed-off-by: Dong Aisheng --- ChangeLog: * No changes --- Documentation/devicetree/bindings/serial/fsl-lpuart.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/serial/fsl-lpuart.txt b/Documentation/devicetree/bindings/serial/fsl-lpuart.txt index c95005e..a1252a0 100644 --- a/Documentation/devicetree/bindings/serial/fsl-lpuart.txt +++ b/Documentation/devicetree/bindings/serial/fsl-lpuart.txt @@ -6,6 +6,8 @@ Required properties: on Vybrid vf610 SoC with 8-bit register organization - "fsl,ls1021a-lpuart" for lpuart compatible with the one integrated on LS1021A SoC with 32-bit big-endian register organization + - "fsl,imx7ulp-lpuart" for lpuart compatible with the one integrated + on i.MX7ULP SoC with 32-bit little-endian register organization - reg : Address and length of the register set for the device - interrupts : Should contain uart interrupt - clocks : phandle + clock specifier pairs, one for each entry in clock-names