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Mon, 18 Sep 2017 10:09:44 +0000 (GMT) X-AuditID: cbfec7f1-f793a6d00000326b-7d-59bf9b6816bf Received: from eusync1.samsung.com ( [203.254.199.211]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id DE.97.20118.76B9FB95; Mon, 18 Sep 2017 11:09:43 +0100 (BST) Received: from AMDC831.digital.local ([106.116.147.122]) by eusync1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0OWH00HHK082V8A0@eusync1.samsung.com>; Mon, 18 Sep 2017 11:09:43 +0100 (BST) From: Andrzej Pietrasiewicz To: linux-samsung-soc@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH 2/2] phy: exynos5-usbdrd: Calibrate LOS levels for exynos5420/5800 Date: Mon, 18 Sep 2017 12:09:31 +0200 Message-id: <1505729371-6509-1-git-send-email-andrzej.p@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1505728934-6200-1-git-send-email-andrzej.p@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrKIsWRmVeSWpSXmKPExsWy7djP87oZs/dHGnzYqW0x62U7i8XGGetZ LY61PWG3mH/kHKtF8+L1bBb9j18zW1x42sNmcf78BnaLTY+vsVrMOL+PyWLRslZmi0NT9zJa rD1yl91i6fWLTBate4+wO/B7rJm3htHj8rWLzB6bVnWyeeyfu4bdY/OSeo++LasYPY7f2M7k 8XmTXABHFJdNSmpOZllqkb5dAlfG2palTAV/nCu2nvFpYNxl3sXIySEhYCIx+e5XNghbTOLC vfVgtpDAUkaJNdfUuxi5gOzPjBIr9+1g7GLkAGvYeSoEIr6MUeLbsX52CKeBSeLxhdWMIN1s AsYSew92MIIkRARaGCXeX+kGq2IWOMss8fDFIWaQKmGBEIkX2/awgtgsAqoSiyeuA7N5BVwk 9r28xgRxk5zEyWOTweKcAq4SV6fuZgIZJCFwn01i7sb3LBBFLhJNk+YzQtjCEq+Ob2GHsGUk Lk/uZoFomMwoseHmByhnO6PE2mMnWCGqrCUOH78IZjML8ElM2jadGeJTXomONiGIEg+Jxuer oModJXre32OBeHoGo8TVH5fZJzBKL2BkWMUoklpanJueWmykV5yYW1yal66XnJ+7iRGYGE7/ O/5xB+P7E1aHGAU4GJV4eDe+3hcpxJpYVlyZe4hRgoNZSYTXsWp/pBBvSmJlVWpRfnxRaU5q 8SFGaQ4WJXFe26i2SCGB9MSS1OzU1ILUIpgsEwenVAOji2feQqPOr1HHUu+VX56TemVizruq D7/yH1glXV6iuWBZQuNsWZ7CuF8+h3QyZ9hvqp/tuTY74Nabdyo/JBauVM9TeNGx49Fxr6lr PtXF63y8UBG1MET/K9+WwFdBin8TV+uufbHmwPrfwe1t9z/aZP1QlHxXs+Fxi1wBr8jJr6/v vXA6/qnxuhJLcUaioRZzUXEiALSBWzUIAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrBLMWRmVeSWpSXmKPExsVy+t/xy7oZs/dHGrRwWcx62c5isXHGelaL Y21P2C3mHznHatG8eD2bRf/j18wWF572sFmcP7+B3WLT42usFjPO72OyWLSsldni0NS9jBZr j9xlt1h6/SKTReveI+wO/B5r5q1h9Lh87SKzx6ZVnWwe++euYffYvKTeo2/LKkaP4ze2M3l8 3iQXwBHFZZOSmpNZllqkb5fAlbG2ZSlTwR/niq1nfBoYd5l3MXJwSAiYSOw8FdLFyAlkiklc uLeerYuRi0NIYAmjxN9JW1khnCYmiZ/PzrOCVLEJGEvsPdjBCJIQEWhhlOi8uAXMYRY4zyzR 8mUBI0iVsECIxItte8A6WARUJRZPXAdm8wq4SOx7eY0JYp+cxMljk8HinAKuElen7gaLCwHV HO/qYZrAyLuAkWEVo0hqaXFuem6xkV5xYm5xaV66XnJ+7iZGYPhuO/Zzyw7GrnfBhxgFOBiV eHg3vN4XKcSaWFZcmXuIUYKDWUmE17Fqf6QQb0piZVVqUX58UWlOavEhRmkOFiVx3t49qyOF BNITS1KzU1MLUotgskwcnFINjFeNnKqqTzDacza/fVCftmder0yC5NW6Tcn7/ed3B6l3pilH pE7awZqiVyy+T/88E5uvOPv1LU7K0wNXvt7ReuvzF76bbacY7adqtfjwyx9tf9a/TLb+4Zdz 4feu79DiPC74dunm3HPPN95y8rdnmFMfa/q9+sT7n0/etlud4Ig9ccpL3M+aQYmlOCPRUIu5 qDgRAIpy+VdbAgAA X-CMS-MailID: 20170918100944eucas1p2735d3d6a6ee562b927fb9dfaeb0d4090 X-Msg-Generator: CA X-Sender-IP: 182.198.249.180 X-Local-Sender: =?UTF-8?B?QW5kcnplaiBQaWV0cmFzaWV3aWN6G1NSUE9MLUtlcm5lbCAo?= =?UTF-8?B?VFApG+yCvOyEseyghOyekBtTZW5pb3IgU29mdHdhcmUgRW5naW5lZXI=?= X-Global-Sender: =?UTF-8?B?QW5kcnplaiBUb21hc3ogUGlldHJhc2lld2ljehtTUlBPTC1L?= =?UTF-8?B?ZXJuZWwgKFRQKRtTYW1zdW5nIEVsZWN0cm9uaWNzG1NlbmlvciBTb2Z0d2Fy?= =?UTF-8?B?ZSBFbmdpbmVlcg==?= X-Sender-Code: =?UTF-8?B?QzEwG0VIURtDMTBDRDAyQ0QwMjczOTI=?= CMS-TYPE: 201P X-CMS-RootMailID: 20170918100944eucas1p2735d3d6a6ee562b927fb9dfaeb0d4090 X-RootMTR: 20170918100944eucas1p2735d3d6a6ee562b927fb9dfaeb0d4090 References: <1505728934-6200-1-git-send-email-andrzej.p@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170918_111017_105397_2A23760F X-CRM114-Status: GOOD ( 23.23 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Felipe Balbi , Bartlomiej Zolnierkiewicz , Greg Kroah-Hartman , Russell King , Krzysztof Kozlowski , Kishon Vijay Abraham I , Rob Herring , Kukjin Kim , Andrzej Pietrasiewicz , Marek Szyprowski MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Vivek Gautam Adding phy calibration sequence for USB 3.0 DRD PHY present on Exynos5420/5800 systems. This calibration facilitates setting certain PHY parameters viz. the Loss-of-Signal (LOS) Detector Threshold Level, as well as Tx-Vboost-Level for Super-Speed operations. Additionally we also set proper time to wait for RxDetect measurement, for desired PHY reference clock, so as to solve issue with enumeration of few USB 3.0 devices, like Samsung SUM-TSB16S 3.0 USB drive on the controller. We are using CR_port for this purpose to send required data to override the LOS values. On testing with USB 3.0 devices on USB 3.0 port present on SMDK5420, and peach-pit boards should see following message: usb 2-1: new SuperSpeed USB device number 2 using xhci-hcd and without this patch, should see below shown message: usb 1-1: new high-speed USB device number 2 using xhci-hcd [Also removed unnecessary extra lines in the register macro definitions] Signed-off-by: Vivek Gautam [adapted to use phy_reset as entry point] Signed-off-by: Andrzej Pietrasiewicz --- drivers/phy/samsung/phy-exynos5-usbdrd.c | 183 +++++++++++++++++++++++++++++++ drivers/usb/dwc3/core.c | 8 +- 2 files changed, 189 insertions(+), 2 deletions(-) diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c index 7c41daa..f7de067 100644 --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c @@ -89,7 +89,17 @@ #define PHYCLKRST_COMMONONN BIT(0) #define EXYNOS5_DRD_PHYREG0 0x14 +#define PHYREG0_SSC_REF_CLK_SEL BIT(21) +#define PHYREG0_SSC_RANGE BIT(20) +#define PHYREG0_CR_WRITE BIT(19) +#define PHYREG0_CR_READ BIT(18) +#define PHYREG0_CR_DATA_IN(_x) ((_x) << 2) +#define PHYREG0_CR_CAP_DATA BIT(1) +#define PHYREG0_CR_CAP_ADDR BIT(0) + #define EXYNOS5_DRD_PHYREG1 0x18 +#define PHYREG1_CR_DATA_OUT(_x) ((_x) << 1) +#define PHYREG1_CR_ACK BIT(0) #define EXYNOS5_DRD_PHYPARAM0 0x1c @@ -118,6 +128,25 @@ #define EXYNOS5_DRD_PHYRESUME 0x34 #define EXYNOS5_DRD_LINKPORT 0x44 +/* USB 3.0 DRD PHY SS Function Control Reg; accessed by CR_PORT */ +#define EXYNOS5_DRD_PHYSS_LOSLEVEL_OVRD_IN (0x15) +#define LOSLEVEL_OVRD_IN_LOS_BIAS_5420 (0x5 << 13) +#define LOSLEVEL_OVRD_IN_LOS_BIAS_DEFAULT (0x0 << 13) +#define LOSLEVEL_OVRD_IN_EN (0x1 << 10) +#define LOSLEVEL_OVRD_IN_LOS_LEVEL_DEFAULT (0x9 << 0) + +#define EXYNOS5_DRD_PHYSS_TX_VBOOSTLEVEL_OVRD_IN (0x12) +#define TX_VBOOSTLEVEL_OVRD_IN_VBOOST_5420 (0x5 << 13) +#define TX_VBOOSTLEVEL_OVRD_IN_VBOOST_DEFAULT (0x4 << 13) + +#define EXYNOS5_DRD_PHYSS_LANE0_TX_DEBUG (0x1010) +#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_19M2_20M (0x4 << 4) +#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_24M (0x8 << 4) +#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_25M_26M (0x8 << 4) +#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_48M_50M_52M (0x20 << 4) +#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_62M5 (0x20 << 4) +#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_96M_100M (0x40 << 4) + #define KHZ 1000 #define MHZ (KHZ * KHZ) @@ -526,6 +555,151 @@ static int exynos5_usbdrd_phy_power_off(struct phy *phy) return 0; } +static int crport_handshake(struct exynos5_usbdrd_phy *phy_drd, + u32 val, u32 cmd) +{ + u32 usec = 100; + unsigned int result; + + writel(val | cmd, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0); + + do { + result = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYREG1); + if (result & PHYREG1_CR_ACK) + break; + + udelay(1); + } while (usec-- > 0); + + if (!usec) { + dev_err(phy_drd->dev, + "CRPORT handshake timeout1 (0x%08x)\n", val); + return -ETIME; + } + + usec = 100; + + writel(val, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0); + + do { + result = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYREG1); + if (!(result & PHYREG1_CR_ACK)) + break; + + udelay(1); + } while (usec-- > 0); + + if (!usec) { + dev_err(phy_drd->dev, + "CRPORT handshake timeout2 (0x%08x)\n", val); + return -ETIME; + } + + return 0; +} + +static int crport_ctrl_write(struct exynos5_usbdrd_phy *phy_drd, + u32 addr, u32 data) +{ + int ret; + + /* Write Address */ + writel(PHYREG0_CR_DATA_IN(addr), + phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0); + ret = crport_handshake(phy_drd, PHYREG0_CR_DATA_IN(addr), + PHYREG0_CR_CAP_ADDR); + if (ret) + return ret; + + /* Write Data */ + writel(PHYREG0_CR_DATA_IN(data), + phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0); + ret = crport_handshake(phy_drd, PHYREG0_CR_DATA_IN(data), + PHYREG0_CR_CAP_DATA); + if (ret) + return ret; + + ret = crport_handshake(phy_drd, PHYREG0_CR_DATA_IN(data), + PHYREG0_CR_WRITE); + + return ret; +} + +/* + * Calibrate few PHY parameters using CR_PORT register to meet + * SuperSpeed requirements on Exynos5420 and Exynos5800 systems, + * which have 28nm USB 3.0 DRD PHY. + */ +static int exynos5420_usbdrd_phy_calibrate(struct exynos5_usbdrd_phy *phy_drd) +{ + unsigned int temp; + int ret = 0; + + /* + * Change los_bias to (0x5) for 28nm PHY from a + * default value (0x0); los_level is set as default + * (0x9) as also reflected in los_level[30:26] bits + * of PHYPARAM0 register. + */ + temp = LOSLEVEL_OVRD_IN_LOS_BIAS_5420 | + LOSLEVEL_OVRD_IN_EN | + LOSLEVEL_OVRD_IN_LOS_LEVEL_DEFAULT; + ret = crport_ctrl_write(phy_drd, + EXYNOS5_DRD_PHYSS_LOSLEVEL_OVRD_IN, + temp); + if (ret) { + dev_err(phy_drd->dev, + "Failed setting Loss-of-Signal level for SuperSpeed\n"); + return ret; + } + + /* + * Set tx_vboost_lvl to (0x5) for 28nm PHY Tuning, + * to raise Tx signal level from its default value of (0x4) + */ + temp = TX_VBOOSTLEVEL_OVRD_IN_VBOOST_5420; + ret = crport_ctrl_write(phy_drd, + EXYNOS5_DRD_PHYSS_TX_VBOOSTLEVEL_OVRD_IN, + temp); + if (ret) { + dev_err(phy_drd->dev, + "Failed setting Tx-Vboost-Level for SuperSpeed\n"); + return ret; + } + + /* + * Set proper time to wait for RxDetect measurement, for + * desired reference clock of PHY, by tuning the CR_PORT + * register LANE0.TX_DEBUG which is internal to PHY. + * This fixes issue with few USB 3.0 devices, which are + * not detected (not even generate interrupts on the bus + * on insertion) without this change. + * e.g. Samsung SUM-TSB16S 3.0 USB drive. + */ + switch (phy_drd->extrefclk) { + case EXYNOS5_FSEL_50MHZ: + temp = LANE0_TX_DEBUG_RXDET_MEAS_TIME_48M_50M_52M; + break; + case EXYNOS5_FSEL_20MHZ: + case EXYNOS5_FSEL_19MHZ2: + temp = LANE0_TX_DEBUG_RXDET_MEAS_TIME_19M2_20M; + break; + case EXYNOS5_FSEL_24MHZ: + default: + temp = LANE0_TX_DEBUG_RXDET_MEAS_TIME_24M; + break; + } + + ret = crport_ctrl_write(phy_drd, + EXYNOS5_DRD_PHYSS_LANE0_TX_DEBUG, + temp); + if (ret) + dev_err(phy_drd->dev, + "Failed setting RxDetect measurement time for SuperSpeed\n"); + + return ret; +} + static struct phy *exynos5_usbdrd_phy_xlate(struct device *dev, struct of_phandle_args *args) { @@ -537,11 +711,20 @@ static struct phy *exynos5_usbdrd_phy_xlate(struct device *dev, return phy_drd->phys[args->args[0]].phy; } +static int exynos5_usbdrd_phy_reset(struct phy *phy) +{ + struct phy_usb_instance *inst = phy_get_drvdata(phy); + struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst); + + return exynos5420_usbdrd_phy_calibrate(phy_drd); +} + static const struct phy_ops exynos5_usbdrd_phy_ops = { .init = exynos5_usbdrd_phy_init, .exit = exynos5_usbdrd_phy_exit, .power_on = exynos5_usbdrd_phy_power_on, .power_off = exynos5_usbdrd_phy_power_off, + .reset = exynos5_usbdrd_phy_reset, .owner = THIS_MODULE, }; diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 03474d3..1d5836e 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -156,9 +156,10 @@ static void __dwc3_set_mode(struct work_struct *work) } else { if (dwc->usb2_phy) otg_set_vbus(dwc->usb2_phy->otg, true); - if (dwc->usb2_generic_phy) + if (dwc->usb2_generic_phy) { phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); - + phy_reset(dwc->usb2_generic_phy); + } } break; case DWC3_GCTL_PRTCAP_DEVICE: @@ -955,6 +956,9 @@ static int dwc3_core_init_mode(struct dwc3 *dwc) dev_err(dev, "failed to initialize host\n"); return ret; } + + if (dwc->usb2_generic_phy) + phy_reset(dwc->usb2_generic_phy); break; case USB_DR_MODE_OTG: INIT_WORK(&dwc->drd_work, __dwc3_set_mode);