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Wed, 04 Oct 2017 15:25:26 -0700 (PDT) From: Bryan O'Donoghue To: richard.leitner@skidata.com, srinivas.kandagatla@linaro.org, axel.lin@ingics.com, ping.bai@nxp.com, d.schultz@phytec.de, peng.fan@nxp.com, van.freenix@gmail.com, p.zabel@pengutronix.de Subject: [RESEND][PATCH 4/7] nvmem: imx-ocotp: Move i.MX6 write clock setup to dedicated function Date: Wed, 4 Oct 2017 23:25:18 +0100 Message-Id: <1507155921-824-5-git-send-email-pure.logic@nexus-software.ie> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1507155921-824-1-git-send-email-pure.logic@nexus-software.ie> References: <1507155921-824-1-git-send-email-pure.logic@nexus-software.ie> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20171004_152547_487961_F85EECE9 X-CRM114-Status: GOOD ( 13.99 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pure.logic@nexus-software.ie, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The i.MX7S/D has a different set of timing requirements, as a pre-cursor to adding the i.MX7 timing parameters, move the i.MX6 stuff to a dedicated function. Fixes: 0642bac7da42 ("nvmem: imx-ocotp: add write support") Signed-off-by: Bryan O'Donoghue Reviewed-by: Philipp Zabel --- drivers/nvmem/imx-ocotp.c | 47 +++++++++++++++++++++++++++-------------------- 1 file changed, 27 insertions(+), 20 deletions(-) diff --git a/drivers/nvmem/imx-ocotp.c b/drivers/nvmem/imx-ocotp.c index 8034937..0cd7e03 100644 --- a/drivers/nvmem/imx-ocotp.c +++ b/drivers/nvmem/imx-ocotp.c @@ -169,6 +169,31 @@ static int imx_ocotp_read(void *context, unsigned int offset, return ret; } +static void imx_ocotp_set_imx6_timing(struct ocotp_priv *priv) +{ + unsigned long clk_rate = 0; + unsigned long strobe_read, relax, strobe_prog; + u32 timing = 0; + + /* 47.3.1.3.1 + * Program HW_OCOTP_TIMING[STROBE_PROG] and HW_OCOTP_TIMING[RELAX] + * fields with timing values to match the current frequency of the + * ipg_clk. OTP writes will work at maximum bus frequencies as long + * as the HW_OCOTP_TIMING parameters are set correctly. + */ + clk_rate = clk_get_rate(priv->clk); + + relax = clk_rate / (1000000000 / DEF_RELAX) - 1; + strobe_prog = clk_rate / (1000000000 / 10000) + 2 * (DEF_RELAX + 1) - 1; + strobe_read = clk_rate / (1000000000 / 40) + 2 * (DEF_RELAX + 1) - 1; + + timing = strobe_prog & 0x00000FFF; + timing |= (relax << 12) & 0x0000F000; + timing |= (strobe_read << 16) & 0x003F0000; + + writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING); +} + static int imx_ocotp_write(void *context, unsigned int offset, void *val, size_t bytes) { @@ -176,9 +201,6 @@ static int imx_ocotp_write(void *context, unsigned int offset, void *val, u32 *buf = val; int ret; - unsigned long clk_rate = 0; - unsigned long strobe_read, relax, strobe_prog; - u32 timing = 0; u32 ctrl; u8 waddr; u8 word = 0; @@ -197,23 +219,8 @@ static int imx_ocotp_write(void *context, unsigned int offset, void *val, return ret; } - /* 47.3.1.3.1 - * Program HW_OCOTP_TIMING[STROBE_PROG] and HW_OCOTP_TIMING[RELAX] - * fields with timing values to match the current frequency of the - * ipg_clk. OTP writes will work at maximum bus frequencies as long - * as the HW_OCOTP_TIMING parameters are set correctly. - */ - clk_rate = clk_get_rate(priv->clk); - - relax = clk_rate / (1000000000 / DEF_RELAX) - 1; - strobe_prog = clk_rate / (1000000000 / 10000) + 2 * (DEF_RELAX + 1) - 1; - strobe_read = clk_rate / (1000000000 / 40) + 2 * (DEF_RELAX + 1) - 1; - - timing = strobe_prog & 0x00000FFF; - timing |= (relax << 12) & 0x0000F000; - timing |= (strobe_read << 16) & 0x003F0000; - - writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING); + /* Setup the write timing values */ + imx_ocotp_set_imx6_timing(priv); /* 47.3.1.3.2 * Check that HW_OCOTP_CTRL[BUSY] and HW_OCOTP_CTRL[ERROR] are clear.