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bh=WizeQtx7Dtp3uIKDJM65VsBM2w2EO85amzC72OucwZY=; b=eHVh2pKJn16xil6RE3pz62N9E0qcpQT62oe6tUDLAF0dNiqWUgxSJL51EJz2xUhcrz RbufvS5fQvOE7vGJYRMt3y8DAzTygKzY/i89SMS9wY3zKfROHAjNhwi68B7z325llUSL du+R39DSvQeUekrOMTo17T2vpsX+gCMsedYzyOStFDTYxc+GRRA6/sabvcQ+w/XSrOBQ BJnJGQc3WX2HVYhJ3KErfTpaST2vWiWTuyuDPRV/t18MZuOgMOOJiNaC3Vcag9vVJXpL tmSf2r/P1R0Y51VW0+tASUCMU1yTGwSN6VlnH4fxB0K5c/ybBuVxZQ32mu6zTrHFQLAv AJxQ== X-Gm-Message-State: AMCzsaXfho83mJNUYNY57QxAo5sr+gFhYlTHzYQTBWUVQ4pD4Lt8Hm65 GwjxTGUhEmlvc1zmlrKoMDnWbg== X-Google-Smtp-Source: ABhQp+QoT2BvlD3gSxrcinLYSTlUhN6dSp6fLwqg7lSq4EHoZpYXd4kBpOhlcZG1Y5pWbEUylHrRTA== X-Received: by 10.223.164.89 with SMTP id e25mr2540033wra.75.1508225886792; Tue, 17 Oct 2017 00:38:06 -0700 (PDT) Received: from localhost.localdomain ([90.63.244.31]) by smtp.gmail.com with ESMTPSA id o18sm14679106wrc.45.2017.10.17.00.38.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 17 Oct 2017 00:38:06 -0700 (PDT) From: Neil Armstrong To: khilman@baylibre.com, carlo@caione.org Subject: [PATCH 2/2] dt-bindings: power: add amlogic meeson power domain bindings Date: Tue, 17 Oct 2017 09:38:02 +0200 Message-Id: <1508225882-8795-3-git-send-email-narmstrong@baylibre.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1508225882-8795-1-git-send-email-narmstrong@baylibre.com> References: <1508225882-8795-1-git-send-email-narmstrong@baylibre.com> X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Neil Armstrong MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Neil Armstrong --- .../bindings/power/amlogic,meson-gx-pwrc.txt | 65 ++++++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/amlogic,meson-gx-pwrc.txt diff --git a/Documentation/devicetree/bindings/power/amlogic,meson-gx-pwrc.txt b/Documentation/devicetree/bindings/power/amlogic,meson-gx-pwrc.txt new file mode 100644 index 0000000..94c2474 --- /dev/null +++ b/Documentation/devicetree/bindings/power/amlogic,meson-gx-pwrc.txt @@ -0,0 +1,65 @@ +Amlogic Meson Power Controller +============================== + +The Amlogic Meson SoCs embeds an internal Power domain controller. + +VPU Power Domain +---------------- + +The Video Processing Unit power domain is controlled by this power controller, +but the domain requires some external resources to meet the correct power +sequences. +The bindings must respect the power domain bindings as described in the file +power_domain.txt + +Device Tree Bindings: +--------------------- + +Required properties: +- compatible: value should be different for each SoC family as : + - GXBB (S905) : "amlogic,meson-gxbb-vpu" + - GXL (S905X, S905D) : "amlogic,meson-gxl-vpu" + - GXM (S912) : "amlogic,meson-gxm-vpu" + followed by the common "amlogic,meson-gx-vpu" +- #power-domain-cells: should be 0 +- amlogic,hhi-sysctrl: phandle to the HHI sysctrl node +- resets: phandles to the reset lines needed for this power demain sequence + as described in ../reset/reset.txt +- clocks: from common clock binding: handle to VPU and VAPB clocks +- clock-names: from common clock binding: must contain "vpu", "vapb" + corresponding to entry in the clocks property. + +Parent node should have the following properties : +- compatible: "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd" +- reg: base address and size of the AO system control register space. + +Example: +------- + +ao_sysctrl: sys-ctrl@0 { + compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd"; + reg = <0x0 0x0 0x0 0x100>; + + pwrc_vpu: power-controller-vpu { + compatible = "amlogic,meson-gx-pwrc-vpu"; + #power-domain-cells = <0>; + amlogic,hhi-sysctrl = <&sysctrl>; + resets = <&reset RESET_VIU>, + <&reset RESET_VENC>, + <&reset RESET_VCBUS>, + <&reset RESET_BT656>, + <&reset RESET_DVIN_RESET>, + <&reset RESET_RDMA>, + <&reset RESET_VENCI>, + <&reset RESET_VENCP>, + <&reset RESET_VDAC>, + <&reset RESET_VDI6>, + <&reset RESET_VENCL>, + <&reset RESET_VID_LOCK>; + clocks = <&clkc CLKID_VPU>, + <&clkc CLKID_VAPB>; + clock-names = "vpu", "vapb"; + }; +}; + +