From patchwork Mon Dec 11 02:03:42 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shanker Donthineni X-Patchwork-Id: 10104089 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id BF8B7602B3 for ; Mon, 11 Dec 2017 02:04:17 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B16F82936F for ; Mon, 11 Dec 2017 02:04:17 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A334329370; Mon, 11 Dec 2017 02:04:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 3215C2936E for ; Mon, 11 Dec 2017 02:04:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To: References:List-Owner; bh=pt3+7252G0MkgTDw2OOl6hQ888sr2wEgBZV0Dtu/6tM=; b=OJj 9IFMcYoPikvAhFmtvwEvRatPc5P9j6b80Q84hPp3ap6AbYk8cnyOaBEniYFq9kJa05rB5k7Wv8HWo Gz37tQu/uvW4DmCcVdFWH/M55QJCKtrPbWy/ev+rCyDv2+c7cLgdFFtd746HBNuoRXv1OaZlgtL+R FgBQYg7t1dfMbtbj7G/fw3+HPez/Kwkq5JpyLowfUaW7vuefAfVBKbdPx+iuNQxOfza2PcOFS0qXn QsW/htGZI3UgMMp9oKlZ1t/d/Ej8By/37Gg3n05AHfTRdwyP8wF/8juniTpN+cmz56/jRFvhhTRWa EWDleY1Nk7DMYIupwGV0tiIf09hLUOQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1eODS1-0002ys-LB; Mon, 11 Dec 2017 02:04:13 +0000 Received: from smtp.codeaurora.org ([198.145.29.96]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1eODRy-0002vg-K2 for linux-arm-kernel@lists.infradead.org; Mon, 11 Dec 2017 02:04:12 +0000 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 1FBE46083B; Mon, 11 Dec 2017 02:03:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1512957828; bh=ZWBd6W/3LZ7J6JU8CEIFc34fihZIGLWLmm858am7XF8=; h=From:To:Cc:Subject:Date:From; b=htO6fN3SkG11FvZ9spM2Co7h2375xi0WaJyeTe2qWYR5VeSQrxOepuXvBNzLcL3lQ hQDNsf/tMcV4pBN1TQ7rGSMEFtw4zH8m4eVGE7XUl/b7SeKPHbeAckGsAQQ11cP+jF fb4RUFml2a0MOvViVnUkzttjGDr+4ESBUxqC0Yfw= Received: from shankerd-ubuntu.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: shankerd@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 5020A600EC; Mon, 11 Dec 2017 02:03:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1512957827; bh=ZWBd6W/3LZ7J6JU8CEIFc34fihZIGLWLmm858am7XF8=; h=From:To:Cc:Subject:Date:From; b=ImZaOAgXNeDIKzAbrdh97sO61jx2y/NEjnJrwf5TeBwCYY1J/FiD6r8bTPMnVqX+A asou6O9W5olcqWyPXr9vDMZ4tbpnAvCHGGTndz4jVcC82XCeCIl8JFYfNFi1UmSBxh 57gUnurxVg/JoVpFXhEu0RXO3oXdSbd71tyA631c= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 5020A600EC Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=shankerd@codeaurora.org From: Shanker Donthineni To: Will Deacon , Marc Zyngier , linux-arm-kernel@lists.infradead.org Subject: [RESEND PATCH v4 1/2] arm64: Define cputype macros for Falkor CPU Date: Sun, 10 Dec 2017 20:03:42 -0600 Message-Id: <1512957823-18064-1-git-send-email-shankerd@codeaurora.org> X-Mailer: git-send-email 1.9.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20171210_180410_736255_2E4A3A93 X-CRM114-Status: UNSURE ( 9.13 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-efi@vger.kernel.org, Ard Biesheuvel , Matt Fleming , Catalin Marinas , linux-kernel@vger.kernel.org, James Morse , Shanker Donthineni , Robin Murphy , kvmarm@lists.cs.columbia.edu, Christoffer Dall MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add cputype definition macros for Qualcomm Datacenter Technologies Falkor CPU in cputype.h. It's unfortunate that the first revision of the Falkor CPU used the wrong part number 0x800, got fixed in v2 chip with part number 0xC00, and would be used the same value for future revisions. Signed-off-by: Shanker Donthineni --- arch/arm64/include/asm/cputype.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 235e77d..cbf08d7 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -91,6 +91,7 @@ #define BRCM_CPU_PART_VULCAN 0x516 #define QCOM_CPU_PART_FALKOR_V1 0x800 +#define QCOM_CPU_PART_FALKOR 0xC00 #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57) @@ -99,6 +100,7 @@ #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX) #define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1) +#define MIDR_QCOM_FALKOR MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR) #ifndef __ASSEMBLY__