From patchwork Thu Dec 28 14:40:37 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ulf Hansson X-Patchwork-Id: 10134921 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 736BC60212 for ; Thu, 28 Dec 2017 14:41:14 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 63D232D4C5 for ; Thu, 28 Dec 2017 14:41:14 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 57E012D5DF; Thu, 28 Dec 2017 14:41:14 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id CDC9E2D4C5 for ; Thu, 28 Dec 2017 14:41:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To: References:List-Owner; bh=FaCexXy/NaXCtn7US8R7YHenx2QKKHN229DPieJppqQ=; b=MeL qM9mmIpyfZpwPRacgkAVdvBSt+ZOkNoHaQIqnSrWi2svTR/c0jvQKgI7kVBqyGHJ/TkKux6PJb2DE aWbfz5KNiQFxVXlYbUWJRnpqm62YWgEQCf9eqqXGrULyYQbIkRj2zLN2vdA/vrfC4Gv9u8noKwag+ tAHCSHV03GLjjNMqHsx5n5758od4svLvOyvHAV/XSm/D0L2hLj98t8qpXTMdqnb3MoyMbTiiQxBvM P8K80rDEgY6AYuFj1Oj5YWfOMbQc8ZItBmT8VBYvPptU5wgKfEzvX4lt2WkdzlHESFzwwn1MI309g 4JWY59vFxg5CLtk/ahJEuqp/6n/IT2w==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.89 #1 (Red Hat Linux)) id 1eUZMt-0008Kt-Kg; Thu, 28 Dec 2017 14:41:11 +0000 Received: from mail-lf0-x241.google.com ([2a00:1450:4010:c07::241]) by bombadil.infradead.org with esmtps (Exim 4.89 #1 (Red Hat Linux)) id 1eUZMo-0008IZ-UZ for linux-arm-kernel@lists.infradead.org; Thu, 28 Dec 2017 14:41:09 +0000 Received: by mail-lf0-x241.google.com with SMTP id y78so39826690lfd.1 for ; Thu, 28 Dec 2017 06:40:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=0aZTYNHi2keQmBQx1r07kzof4IVMXRZtLqTWpHBqUpg=; b=eJxv4kqKGV3RsQ4jmhsxd+7C3Hut5nFpXuBw+GHmb5pgBgN5+JtrKC6ZX/zYfD978Z AfXinMkytLBkVVJFmEe1U7S+pexgNQwPCOwYrhinvLkq8/mBOceuiNEQxnGK4Ym5tB6i rmsJWFuWK5aDIVsZ1YUdIHRXExAtIYX6mL0ac= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=0aZTYNHi2keQmBQx1r07kzof4IVMXRZtLqTWpHBqUpg=; b=qxyA572tpgAqX9cukD6SI5PEqUw/b6xVTlhNEkhoP9IRVzGJ85xUSF3rhUS75WV0xB ETF0lu18RkbqiJZOvvzHnO1aGuYuv1tjj07ZKuLiwwAAyT/TcaDcplQNpyjKPGZGsm4j BkkhpL/FuFb0g4YknoBUJKInh3MPNHMiEV49jDYj8GMkv38pKNQxbWNOnzY4FlxjKkED JExxvzvsz7hOoK2Sid84pHn7pSl+dQsUvKyP5IvU7oDZzSz7Iz3+vM1O6GEPvNDqG95E h/5hKqwosO3DS+2njKaWpq2Jr/pMFWKm8rUC5aCsnWEGCkZQxvq0A1EjdSbHO0yZT/+f rfsg== X-Gm-Message-State: AKGB3mJdwMK1Pj1jSjk1WOqtxWmK03DYghmcijhGsoZ86x1uFV5LG2Pd fGLpa0jFXoK3HozWip+l85nfTQ== X-Google-Smtp-Source: ACJfBovyuMUJgGumPA+xG7wLEKS5OFIyKz8MJMYK00Vhg61S1CLTDIEMtZZad+33ubFCSs+1uX8u5Q== X-Received: by 10.25.215.11 with SMTP id o11mr8088696lfg.33.1514472054230; Thu, 28 Dec 2017 06:40:54 -0800 (PST) Received: from localhost.localdomain (h-158-174-22-67.NA.cust.bahnhof.se. [158.174.22.67]) by smtp.gmail.com with ESMTPSA id c1sm6825104ljb.78.2017.12.28.06.40.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 28 Dec 2017 06:40:53 -0800 (PST) From: Ulf Hansson To: Rob Herring , Mark Rutland , devicetree@vger.kernel.org Subject: [PATCH v2] dt: psci: Update DT bindings to support hierarchical PSCI states Date: Thu, 28 Dec 2017 15:40:37 +0100 Message-Id: <1514472037-25969-1-git-send-email-ulf.hansson@linaro.org> X-Mailer: git-send-email 2.7.4 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20171228_064107_014131_CAF2591E X-CRM114-Status: GOOD ( 12.47 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ulf Hansson , Lorenzo Pieralisi , Kevin Hilman , linux-kernel@vger.kernel.org, Brendan Jackman , linux-arm-kernel@lists.infradead.org, Sudeep Holla , Lina Iyer MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Lina Iyer Update DT bindings to represent hierarchical CPU and CPU domain idle states for PSCI. Also update the PSCI examples to clearly show how flattened and hierarchical idle states can be represented in DT. Signed-off-by: Lina Iyer Signed-off-by: Ulf Hansson Reviewed-by: Rob Herring --- Changes in v2: - Addressed comments from Rob. - Updated some labels in the examples to get more consistency. For your information, I have picked up the work from Lina Iyer around the so called CPU cluster idling series [1,2] and I working on new versions. However, I decided to post the updates to the PSCI DT bindings first, as they will be needed to be agreed upon before further changes can be done to the PSCI firmware driver. Note, these bindings have been discussed over and over again, at LKML, but especially also at various Linux conferences, like LPC and Linaro Connect. We finally came to a conclusion and the changes we agreed upon, should be reflected in this update. Of course, it's a while ago since the latest discussions, but hopefully people don't have too hard time to remember. Kind regards Uffe [1] https://www.spinics.net/lists/arm-kernel/msg566200.html [2] https://lwn.net/Articles/716300/ --- Documentation/devicetree/bindings/arm/psci.txt | 152 +++++++++++++++++++++++++ 1 file changed, 152 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/psci.txt b/Documentation/devicetree/bindings/arm/psci.txt index a2c4f1d..8a09bd2 100644 --- a/Documentation/devicetree/bindings/arm/psci.txt +++ b/Documentation/devicetree/bindings/arm/psci.txt @@ -105,7 +105,159 @@ Case 3: PSCI v0.2 and PSCI v0.1. ... }; +PSCI v1.0 onwards, supports OS-Initiated mode for powering off CPUs and CPU +clusters from the firmware. For such topologies the PSCI firmware driver acts +as pseudo-controller, which may be specified in the psci DT node. The +definitions of the CPU and the CPU cluster topology, must conform to the domain +idle state specification [3]. The domain idle states themselves, must be +compatible with the defined 'domain-idle-state' binding [1], and also need to +specify the arm,psci-suspend-param property for each idle state. + +DT allows representing CPU and CPU cluster idle states in two different ways - + +The flattened model as given in Example 1, lists CPU's idle states followed by +the domain idle state that the CPUs may choose. This is the general practice +followed in PSCI firmwares that support Platform Coordinated mode. Note that +the idle states are all compatible with "arm,idle-state". + +Example 2 represents the hierarchical model of CPU and domain idle states. +CPUs define their domain provider in their DT node. The domain controls the +power to the CPU and possibly other h/w blocks that would be powered off when +the CPU is powered off. The CPU's idle states may therefore be considered as +the domain's idle states and have the compatible "arm,idle-state". Such domains +may be embedded within another domain that represents common h/w blocks between +these CPUs viz. the cluster. The idle states of the cluster would be +represented as the domain's idle states. In order to use OS-Initiated mode of +PSCI in the firmware, the hierarchical representation must be used. + +Example 1: Flattened representation of CPU and domain idle states + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0>; + enable-method = "psci"; + cpu-idle-states = <&CPU_PWRDN>, <&CLUSTER_RET>, + <&CLUSTER_PWRDN>; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x100>; + enable-method = "psci"; + cpu-idle-states = <&CPU_PWRDN>, <&CLUSTER_RET>, + <&CLUSTER_PWRDN>; + }; + + idle-states { + CPU_PWRDN: cpu-power-down { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x000001>; + entry-latency-us = <10>; + exit-latency-us = <10>; + min-residency-us = <100>; + }; + + CLUSTER_RET: cluster-retention { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x1000010>; + entry-latency-us = <500>; + exit-latency-us = <500>; + min-residency-us = <2000>; + }; + + CLUSTER_PWRDN: cluster-power-down { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x1000030>; + entry-latency-us = <2000>; + exit-latency-us = <2000>; + min-residency-us = <6000>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + +Example 2: Hierarchical representation of CPU and domain idle states + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0>; + enable-method = "psci"; + power-domains = <&CPU_PD0>; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x100>; + enable-method = "psci"; + power-domains = <&CPU_PD1>; + }; + + idle-states { + CPU_PWRDN: cpu-power-down { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x000001>; + entry-latency-us = <10>; + exit-latency-us = <10>; + min-residency-us = <100>; + }; + + CLUSTER_RET: cluster-retention { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x1000010>; + entry-latency-us = <500>; + exit-latency-us = <500>; + min-residency-us = <2000>; + }; + + CLUSTER_PWRDN: cluster-power-down { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x1000030>; + entry-latency-us = <2000>; + exit-latency-us = <2000>; + min-residency-us = <6000>; + }; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + CPU_PD0: cpu-pd0 { + #power-domain-cells = <0>; + domain-idle-states = <&CPU_PWRDN>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD1: cpu-pd1 { + #power-domain-cells = <0>; + domain-idle-states = <&CPU_PWRDN>; + power-domains = <&CLUSTER_PD>; + }; + + CLUSTER_PD: cluster-pd { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>; + }; + }; + [1] Kernel documentation - ARM idle states bindings Documentation/devicetree/bindings/arm/idle-states.txt [2] Power State Coordination Interface (PSCI) specification http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf +[3]. PM Domains description + Documentation/devicetree/bindings/power/power_domain.txt