From patchwork Sat Feb 24 00:19:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Saravana Kannan X-Patchwork-Id: 10240065 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id F22AD6056E for ; Sat, 24 Feb 2018 00:20:45 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E06B029A92 for ; Sat, 24 Feb 2018 00:20:45 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CEB6329A9D; Sat, 24 Feb 2018 00:20:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 4F29B29A92 for ; Sat, 24 Feb 2018 00:20:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=gpAxlZkoK46s/dGhewrayUqZAGYxCALEVommqsH70+Y=; b=bLYBCSwhwSv2rdC1EgHTzfMxoF WahMfH4Y9NF7nGZXpcOzwo33sfyzgLESRLzo5Zi1AL8Rt3boJoPbTzfbNCpAP+NtP+VVtrftGZ/V7 7N9qzm8XQSPbGig0cNQNi3172vxxJ3x9Ji7KRkNZzK24tF9ueyomkavxC4z7+J6U8dn7OTn/jfTsm 5okPJV1oYd6mViWPpkHknf5UQOcnL1u5z6o2XuEoVEL2GMHG8iHJfyaiSnL7JMWnVbH+N8ekUcC2g XcrkR8bwJcXEUhNs2OwA7BJFn+olg37NHNQv6+n42Uyaahlsk8TAJjlT/klH/fei+cK570E9egIAR XG0e3iBA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.89 #1 (Red Hat Linux)) id 1epNZo-000069-8R; Sat, 24 Feb 2018 00:20:32 +0000 Received: from smtp.codeaurora.org ([198.145.29.96]) by bombadil.infradead.org with esmtps (Exim 4.89 #1 (Red Hat Linux)) id 1epNZF-0007IF-QM for linux-arm-kernel@lists.infradead.org; Sat, 24 Feb 2018 00:19:59 +0000 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 225CC60F6B; Sat, 24 Feb 2018 00:19:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1519431586; bh=W09lFgjXsnIveq368KsE8chNpG6OoYswKCD+Qie9kbg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=eKGVnPUc5+dERBN/UfhbWPqHGwCHJ4UNA0Q9RPY7gq6YUB6sXaD4RVlsNFGZMDbST fPhwWaOtCekzj77wnQBNkgxjaghgMxhV3UGWPqbIzuHw1vIh5X8INFvmZYeRZlrSsR EzocTe3W27ckgcuhb0M54v3SDfHof6p1qDHldUsg= Received: from skannan1-linux.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: skannan@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 4F70A60F6C; Sat, 24 Feb 2018 00:19:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1519431585; bh=W09lFgjXsnIveq368KsE8chNpG6OoYswKCD+Qie9kbg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JiVutdrJ1bCdyoveZgx+fMCn4RpM+yPQ48N34dLYfTDtKFIi9jdCz8EhOEKDg9AOH oBmGwcqddaU4VtKY3a5HztLrqp3AIYg3hnP5bCF+YGcg6YVrj+EOqfV2UCQd9r72Xi dg7v4koYVFV2REndSDaYXmcwnX/ywwAk55uKbdaM= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 4F70A60F6C Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=skannan@codeaurora.org From: Saravana Kannan To: mark.rutland@arm.com, Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Alexander Shishkin , Jiri Olsa , Namhyung Kim Subject: [PATCH v1 2/2] perf/core: Add support for PMUs that can be read from any CPU Date: Fri, 23 Feb 2018 16:19:38 -0800 Message-Id: <1519431578-11995-2-git-send-email-skannan@codeaurora.org> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1519431578-11995-1-git-send-email-skannan@codeaurora.org> References: <1519431578-11995-1-git-send-email-skannan@codeaurora.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180223_161957_903666_4239303A X-CRM114-Status: GOOD ( 15.42 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: skannan@codeaurora.org, avilaj@codeaurora.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Some PMUs events can be read from any CPU. So allow the PMU to mark events as such. For these events, we don't need to reject reads or make smp calls to the event's CPU and cause unnecessary wake ups. Good examples of such events would be events from caches shared across all CPUs. Signed-off-by: Saravana Kannan --- include/linux/perf_event.h | 3 +++ kernel/events/core.c | 10 ++++++++-- 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h index 7546822..ee8978f 100644 --- a/include/linux/perf_event.h +++ b/include/linux/perf_event.h @@ -510,9 +510,12 @@ typedef void (*perf_overflow_handler_t)(struct perf_event *, * PERF_EV_CAP_SOFTWARE: Is a software event. * PERF_EV_CAP_READ_ACTIVE_PKG: A CPU event (or cgroup event) that can be read * from any CPU in the package where it is active. + * PERF_EV_CAP_READ_ANY_CPU: A CPU event (or cgroup event) that can be read + * from any CPU. */ #define PERF_EV_CAP_SOFTWARE BIT(0) #define PERF_EV_CAP_READ_ACTIVE_PKG BIT(1) +#define PERF_EV_CAP_READ_ANY_CPU BIT(2) #define SWEVENT_HLIST_BITS 8 #define SWEVENT_HLIST_SIZE (1 << SWEVENT_HLIST_BITS) diff --git a/kernel/events/core.c b/kernel/events/core.c index 5d3df58..570187b 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -3484,6 +3484,10 @@ static int __perf_event_read_cpu(struct perf_event *event, int event_cpu) { u16 local_pkg, event_pkg; + if (event->group_caps & PERF_EV_CAP_READ_ANY_CPU) { + return smp_processor_id(); + } + if (event->group_caps & PERF_EV_CAP_READ_ACTIVE_PKG) { int local_cpu = smp_processor_id(); @@ -3575,6 +3579,7 @@ int perf_event_read_local(struct perf_event *event, u64 *value, { unsigned long flags; int ret = 0; + bool is_any_cpu = !!(event->group_caps & PERF_EV_CAP_READ_ANY_CPU); /* * Disabling interrupts avoids all counter scheduling (context @@ -3600,7 +3605,8 @@ int perf_event_read_local(struct perf_event *event, u64 *value, /* If this is a per-CPU event, it must be for this CPU */ if (!(event->attach_state & PERF_ATTACH_TASK) && - event->cpu != smp_processor_id()) { + event->cpu != smp_processor_id() && + !is_any_cpu) { ret = -EINVAL; goto out; } @@ -3610,7 +3616,7 @@ int perf_event_read_local(struct perf_event *event, u64 *value, * or local to this CPU. Furthermore it means its ACTIVE (otherwise * oncpu == -1). */ - if (event->oncpu == smp_processor_id()) + if (event->oncpu == smp_processor_id() || is_any_cpu) event->pmu->read(event); *value = local64_read(&event->count);