From patchwork Wed Mar 14 00:50:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shanker Donthineni X-Patchwork-Id: 10281325 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 33DB860231 for ; Wed, 14 Mar 2018 00:50:29 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 256C52865F for ; Wed, 14 Mar 2018 00:50:29 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1A48F28662; Wed, 14 Mar 2018 00:50:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id BD01B2865F for ; Wed, 14 Mar 2018 00:50:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To: References:List-Owner; bh=zeJVr0vL1GjTigiVcD5g+wyF7tZroQ7+zurz8o4/ZIs=; b=Ssy juJOjNcrjVL3AtLF6MUPmdp1ljTCSY+iKO2hWpqV5za3DmeZUOmJ8ONtP297bayVbWLHXkNjZZ2rN 3IJDIv5i+/I+tmwwaNVnFjOGZ68SSML358FelIDRA22eO7nMpLwvuTWJpF3iS+bP8UsDYckWFblzI o2HK7tJclaTNl+rQmPEUGgkVdkzeVMqwawtENG+0CnkKQnslMf3MKGCL1T1hSvygAN93DZaPbG9M0 UZQFh8CJxM/mZ+qfmpTYlABjik1CYguXForpzRlYIB4Lto1ZzR7MqRGj7A8myxasHvNXjMEM+ZERA PgK5uDyUbhId2oi9Z044uvuOQl0z2JQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1evucY-0007VO-Ex; Wed, 14 Mar 2018 00:50:22 +0000 Received: from smtp.codeaurora.org ([198.145.29.96]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1evucT-0006Zy-Tn for linux-arm-kernel@lists.infradead.org; Wed, 14 Mar 2018 00:50:19 +0000 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 830E260591; Wed, 14 Mar 2018 00:50:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1520988605; bh=aFdftBTseoiQGYH5FZ/0PbTh7OAaqne25AMT/+xqzBg=; h=From:To:Cc:Subject:Date:From; b=MY1rT7eBaw71xaU46oX9zBB5tFCw68XD4fQYghrthFXcR7rJ03q3tHcGfbr6wsEfy 3AhEisQuhzfg8ywS/YliOjXYhe552TKHGh1bFvZsT5gj7dykUUb0UuUR7gg8T9p8UN wUiHLIDYaonprH9mlim2TjiQbx/7eMBeR0ma7LuY= Received: from shankerd-ubuntu.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: shankerd@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 39AB160452; Wed, 14 Mar 2018 00:50:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1520988604; bh=aFdftBTseoiQGYH5FZ/0PbTh7OAaqne25AMT/+xqzBg=; h=From:To:Cc:Subject:Date:From; b=NygOn37OhxMShs/yRvjlffMpCQ84nZX5mn6LubOTVbcBnKW9QGi19Slnp6NUlNfdV rOwNJBEDa2ApB2hhsunoGpbNblZ50lw/IkijwqAJCEGZgoZHunLuhirpebmpIkLZLj DhT0SRQ/waCcIn0sLC4xhQhrvUOujiNzjOL7KyXM= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 39AB160452 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=shankerd@codeaurora.org From: Shanker Donthineni To: Marc Zyngier , linux-kernel , linux-arm-kernel Subject: [PATCH] irqchip/gic-v3: Ensure GICR_CTLR.EnableLPI=0 is observed before enabling Date: Tue, 13 Mar 2018 19:50:01 -0500 Message-Id: <1520988601-16705-1-git-send-email-shankerd@codeaurora.org> X-Mailer: git-send-email 1.9.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180313_175018_015034_47FDD872 X-CRM114-Status: GOOD ( 15.40 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Gleixner , Shanker Donthineni , Jason Cooper , Vikram Sethi MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The definition of the GICR_CTLR.RWP control bit was expanded to indicate status of changing GICR_CTLR.EnableLPI from 1 to 0 is being in progress or completed. Software must observe GICR_CTLR.RWP==0 after clearing GICR_CTLR.EnableLPI from 1 to 0 and before writing GICR_PENDBASER and/or GICR_PROPBASER, otherwise behavior is UNPREDICTABLE. Signed-off-by: Shanker Donthineni --- drivers/irqchip/irq-gic-v3-its.c | 30 +++++++++++++++++++++++------- include/linux/irqchip/arm-gic-v3.h | 1 + 2 files changed, 24 insertions(+), 7 deletions(-) diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index 1d3056f..85cd158 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -1875,15 +1875,31 @@ static void its_cpu_init_lpis(void) gic_data_rdist()->pend_page = pend_page; } - /* Disable LPIs */ val = readl_relaxed(rbase + GICR_CTLR); - val &= ~GICR_CTLR_ENABLE_LPIS; - writel_relaxed(val, rbase + GICR_CTLR); - /* - * Make sure any change to the table is observable by the GIC. - */ - dsb(sy); + /* Make sure LPIs are disabled before programming PEND/PROP registers */ + if (val & GICR_CTLR_ENABLE_LPIS) { + u32 count = 1000000; /* 1s! */ + + /* Disable LPIs */ + val &= ~GICR_CTLR_ENABLE_LPIS; + writel_relaxed(val, rbase + GICR_CTLR); + + /* Make sure any change to GICR_CTLR is observable by the GIC */ + dsb(sy); + + /* Wait for GICR_CTLR.RWP==0 or timeout */ + while (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_RWP) { + if (!count) { + pr_err("CPU%d: Failed to disable LPIs\n", + smp_processor_id()); + return; + } + cpu_relax(); + udelay(1); + count--; + }; + } /* set PROPBASE */ val = (page_to_phys(gic_rdists->prop_page) | diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h index c00c4c33..4d5fb60 100644 --- a/include/linux/irqchip/arm-gic-v3.h +++ b/include/linux/irqchip/arm-gic-v3.h @@ -106,6 +106,7 @@ #define GICR_PIDR2 GICD_PIDR2 #define GICR_CTLR_ENABLE_LPIS (1UL << 0) +#define GICR_CTLR_RWP (1UL << 3) #define GICR_TYPER_CPU_NUMBER(r) (((r) >> 8) & 0xffff)