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Wed, 14 Mar 2018 03:20:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1520997645; bh=ZvC795UOT9TwcGkYO+Yxlw0hBkMl/OFOeiBUptXU2SI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BGLMRunNODeNc3s7b9aOP2ip2ihvX3ZauYe29ht3ftTJrLAyswMj4A6970c1YZyux 1LGJyEuIQih/nbjyVx8v9UA35KFcYKK3gpTNeDWeihsM5QKdCZ+O78CLYZomXPpsAW xj+Uly3X6RLq+vTtEDvMKmznhKkWA9+7n8AXBtiU= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org E55DF60854 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=okaya@codeaurora.org From: Sinan Kaya To: netdev@vger.kernel.org, timur@codeaurora.org, sulrich@codeaurora.org Subject: [PATCH 7/7] ixgbevf: eliminate duplicate barriers on weakly-ordered archs Date: Tue, 13 Mar 2018 23:20:28 -0400 Message-Id: <1520997629-17361-7-git-send-email-okaya@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1520997629-17361-1-git-send-email-okaya@codeaurora.org> References: <1520997629-17361-1-git-send-email-okaya@codeaurora.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180313_202049_200971_50179683 X-CRM114-Status: GOOD ( 13.67 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Sinan Kaya , intel-wired-lan@lists.osuosl.org, Jeff Kirsher , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Code includes wmb() followed by writel() in multiple places. writel() already has a barrier on some architectures like arm64. This ends up CPU observing two barriers back to back before executing the register write. Since code already has an explicit barrier call, changing writel() to writel_relaxed(). Signed-off-by: Sinan Kaya --- drivers/net/ethernet/intel/ixgbevf/ixgbevf.h | 5 ++++- drivers/net/ethernet/intel/ixgbevf/ixgbevf_main.c | 7 +++++++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/intel/ixgbevf/ixgbevf.h b/drivers/net/ethernet/intel/ixgbevf/ixgbevf.h index f695242..64d0e0b 100644 --- a/drivers/net/ethernet/intel/ixgbevf/ixgbevf.h +++ b/drivers/net/ethernet/intel/ixgbevf/ixgbevf.h @@ -244,9 +244,12 @@ static inline u16 ixgbevf_desc_unused(struct ixgbevf_ring *ring) return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; } +/* Assumes caller has executed a write barrier to order memory and device + * requests. + */ static inline void ixgbevf_write_tail(struct ixgbevf_ring *ring, u32 value) { - writel(value, ring->tail); + writel_relaxed(value, ring->tail); } #define IXGBEVF_RX_DESC(R, i) \ diff --git a/drivers/net/ethernet/intel/ixgbevf/ixgbevf_main.c b/drivers/net/ethernet/intel/ixgbevf/ixgbevf_main.c index 9b3d43d..0ba7f59 100644 --- a/drivers/net/ethernet/intel/ixgbevf/ixgbevf_main.c +++ b/drivers/net/ethernet/intel/ixgbevf/ixgbevf_main.c @@ -3643,6 +3643,13 @@ static void ixgbevf_tx_map(struct ixgbevf_ring *tx_ring, tx_ring->next_to_use = i; + /* Force memory writes to complete before letting h/w + * know there are new descriptors to fetch. (Only + * applicable for weak-ordered memory model archs, + * such as IA-64). + */ + wmb(); + /* notify HW of packet */ ixgbevf_write_tail(tx_ring, i);