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Wed, 14 Mar 2018 08:48:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521017325; bh=JTd75sWy4cdy0rvDy8u7PbV05IOPC51PAUZ57AZZEfA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Q12wn2gajg8nLQDU5FLsGBu75vWagc6UWs1LJDJlEUCF6R7WWchISbPrNUcRafVdo hwcjjT/Dpfs/qkCcIgcz6NgyexME6zhBDUvV4JXDNeyStEnSj38Oupm13LsjC3HlJC cU4LfaYxjbbWTEtS/Tyx7L67YS7UqbEFP4nAqyK8= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 7A9C960867 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=cpandya@codeaurora.org From: Chintan Pandya To: catalin.marinas@arm.com, will.deacon@arm.com, arnd@arndb.de Subject: [PATCH v1 1/4] asm/tlbflush: Add flush_tlb_pgtable() for ARM64 Date: Wed, 14 Mar 2018 14:18:22 +0530 Message-Id: <1521017305-28518-2-git-send-email-cpandya@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1521017305-28518-1-git-send-email-cpandya@codeaurora.org> References: <1521017305-28518-1-git-send-email-cpandya@codeaurora.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180314_014851_758999_450EA373 X-CRM114-Status: GOOD ( 10.71 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, linux-arch@vger.kernel.org, toshi.kani@hpe.com, ard.biesheuvel@linaro.org, marc.zyngier@arm.com, gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org, kristina.martsenko@arm.com, takahiro.akashi@linaro.org, james.morse@arm.com, Chintan Pandya , tglx@linutronix.de, akpm@linux-foundation.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP ARM64 MMU implements invalidation of TLB for intermediate page tables for perticular VA. This may or may not be available for other arch. So, provide this API hook only for ARM64, for now. Signed-off-by: Chintan Pandya --- arch/arm64/include/asm/tlbflush.h | 5 +++++ include/asm-generic/tlb.h | 6 ++++++ 2 files changed, 11 insertions(+) diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h index 9e82dd7..5f656f0 100644 --- a/arch/arm64/include/asm/tlbflush.h +++ b/arch/arm64/include/asm/tlbflush.h @@ -209,6 +209,11 @@ static inline void __flush_tlb_pgtable(struct mm_struct *mm, dsb(ish); } +static inline void flush_tlb_pgtable(struct mm_struct *mm, + unsigned long uaddr) +{ + __flush_tlb_pgtable(mm, uaddr); +} #endif #endif diff --git a/include/asm-generic/tlb.h b/include/asm-generic/tlb.h index faddde4..7832c0a 100644 --- a/include/asm-generic/tlb.h +++ b/include/asm-generic/tlb.h @@ -295,4 +295,10 @@ static inline void tlb_remove_check_page_size_change(struct mmu_gather *tlb, #define tlb_migrate_finish(mm) do {} while (0) +#ifndef CONFIG_ARM64 +static inline void flush_tlb_pgtable(struct mm_struct *mm, + unsigned long uaddr) +{ +} +#endif #endif /* _ASM_GENERIC__TLB_H */