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Fri, 16 Mar 2018 16:16:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521217007; bh=/Qda46YcE38zYczmpY8gxqR0G7VdLCDkTSGK0ZNKHoU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=EnUfLnZx5C4w5nphSaQUoyU4wOLAaLOR/Wenjw/ncf5dYvU8InKp4hNW34nQd8Jm1 uPrgJnYg3gW+OjnE3ZlOC8FMuQrRR26c3rMgM0C3Gra6iKgV1Txr3h7p2nZHhvfbyO N1oO5JZxDiZtirqLXpx/q03hMNlanc3EOj6S7EjE= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 8451C60C54 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=okaya@codeaurora.org From: Sinan Kaya To: netdev@vger.kernel.org, timur@codeaurora.org, sulrich@codeaurora.org Subject: [PATCH v3 02/18] ixgbe: eliminate duplicate barriers on weakly-ordered archs Date: Fri, 16 Mar 2018 12:16:15 -0400 Message-Id: <1521216991-28706-3-git-send-email-okaya@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1521216991-28706-1-git-send-email-okaya@codeaurora.org> References: <1521216991-28706-1-git-send-email-okaya@codeaurora.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180316_121656_223751_6A9EBCCC X-CRM114-Status: GOOD ( 12.42 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Sinan Kaya , intel-wired-lan@lists.osuosl.org, Jeff Kirsher , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Code includes wmb() followed by writel() in multiple places. writel() already has a barrier on some architectures like arm64. This ends up CPU observing two barriers back to back before executing the register write. Since code already has an explicit barrier call, changing writel() to writel_relaxed(). Signed-off-by: Sinan Kaya --- drivers/net/ethernet/intel/ixgbe/ixgbe_main.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c index 0da5aa2..58ed70f 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c @@ -1692,7 +1692,7 @@ void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count) * such as IA-64). */ wmb(); - writel(i, rx_ring->tail); + writel_relaxed(i, rx_ring->tail); } } @@ -2453,7 +2453,7 @@ static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, * know there are new descriptors to fetch. */ wmb(); - writel(ring->next_to_use, ring->tail); + writel_relaxed(ring->next_to_use, ring->tail); xdp_do_flush_map(); } @@ -8078,7 +8078,7 @@ static int ixgbe_tx_map(struct ixgbe_ring *tx_ring, ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED); if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) { - writel(i, tx_ring->tail); + writel_relaxed(i, tx_ring->tail); /* we need this if more than one processor can write to our tail * at a time, it synchronizes IO on IA64/Altix systems @@ -10014,7 +10014,7 @@ static void ixgbe_xdp_flush(struct net_device *dev) * are new descriptors to fetch. */ wmb(); - writel(ring->next_to_use, ring->tail); + writel_relaxed(ring->next_to_use, ring->tail); return; }