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Tue, 20 Mar 2018 02:50:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521514220; bh=jQZTqieZcLriv2HRSE7I8uYGB92GghxDNdQO7u3qq20=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VkDHCfgEnj0qqRkL2wQ/CL6tOUgdAYLm9slQpy0CNAjEVBxkkWI/CBs1P13gd3onN Q+vNBvBlofIkVxRfi1Abqzva1kZ9ukVr9hefa+WYgvP8utGp+uZT18MpZAb77LJEVU j2hgDdXUk7ppqjYFW8DLxqofK7Y2Sz8WvnOYMDAk= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org C59DC60FEF Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=okaya@codeaurora.org From: Sinan Kaya To: linux-scsi@vger.kernel.org, timur@codeaurora.org, sulrich@codeaurora.org Subject: [PATCH v4 4/7] scsi: lpfc: Eliminate duplicate barriers on weakly-ordered archs Date: Mon, 19 Mar 2018 22:50:04 -0400 Message-Id: <1521514207-10695-5-git-send-email-okaya@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1521514207-10695-1-git-send-email-okaya@codeaurora.org> References: <1521514207-10695-1-git-send-email-okaya@codeaurora.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180319_225033_833546_D6C266F5 X-CRM114-Status: GOOD ( 12.97 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Dick Kennedy , "Martin K. Petersen" , linux-arm-msm@vger.kernel.org, James Smart , linux-kernel@vger.kernel.org, Sinan Kaya , "James E.J. Bottomley" , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Code includes barrier() followed by writel(). writel() already has a barrier on some architectures like arm64. This ends up CPU observing two barriers back to back before executing the register write. Since code already has an explicit barrier call, changing writel() to writel_relaxed(). Signed-off-by: Sinan Kaya --- drivers/scsi/lpfc/lpfc_sli.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/scsi/lpfc/lpfc_sli.c b/drivers/scsi/lpfc/lpfc_sli.c index 5f5528a..7dae7d3 100644 --- a/drivers/scsi/lpfc/lpfc_sli.c +++ b/drivers/scsi/lpfc/lpfc_sli.c @@ -1647,7 +1647,7 @@ lpfc_sli_update_full_ring(struct lpfc_hba *phba, struct lpfc_sli_ring *pring) * Set ring 'ringno' to SET R0CE_REQ in Chip Att register. * The HBA will tell us when an IOCB entry is available. */ - writel((CA_R0ATT|CA_R0CE_REQ) << (ringno*4), phba->CAregaddr); + writel_relaxed((CA_R0ATT|CA_R0CE_REQ) << (ringno*4), phba->CAregaddr); readl(phba->CAregaddr); /* flush */ pring->stats.iocb_cmd_full++; @@ -1672,7 +1672,7 @@ lpfc_sli_update_ring(struct lpfc_hba *phba, struct lpfc_sli_ring *pring) */ if (!(phba->sli3_options & LPFC_SLI3_CRP_ENABLED)) { wmb(); - writel(CA_R0ATT << (ringno * 4), phba->CAregaddr); + writel_relaxed(CA_R0ATT << (ringno * 4), phba->CAregaddr); readl(phba->CAregaddr); /* flush */ } }