From patchwork Tue Mar 20 22:14:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Isaac J. Manjarres" X-Patchwork-Id: 10298059 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 29CF8602B3 for ; Tue, 20 Mar 2018 22:14:48 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 041B629150 for ; Tue, 20 Mar 2018 22:14:48 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id EB4F92963A; Tue, 20 Mar 2018 22:14:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 7051429150 for ; Tue, 20 Mar 2018 22:14:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To: References:List-Owner; bh=up2SEEEZcWuXh/o+qaZYdwUTgF0xY05o/c2QoP7MpA0=; b=UW5 pyzztSn6OyWLyP9OczMstr/qFFml8o8fkVIXbZLU96dfwoYQsQNXiGZML3pqUFDSMDOo5WAoiVyb6 AiSR5Rv62YwelHg1ofmTsNrTaqjdLl+t/ieJvV70Nih5eOou0vDpUm/457RTK5WnlRmU8olsMhhZ8 fDAJ3b3W0hg0Ze67jJQ3el7ZKAsD+O5mbrE3jvoCtRDYZ7MPiDr5O+O0lZlhkCWwfFIbwkQXv3OFf /bSRsBqkiMG9rYEzqCNS5IywigYgE7aDqmL8FHrVeXfZJpAzyAZE0efSnHhk8pKmSOhkNtpYKjtz1 TV0q+VGVMsdGgiWWTJIfpaEzDLtBnNg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1eyPWl-0007rk-AC; Tue, 20 Mar 2018 22:14:43 +0000 Received: from smtp.codeaurora.org ([198.145.29.96]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1eyPWg-0007qU-VG for linux-arm-kernel@lists.infradead.org; Tue, 20 Mar 2018 22:14:40 +0000 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 94DC06081C; Tue, 20 Mar 2018 22:14:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521584067; bh=zvhu6sYoQC4hMm+uuPQ1DxbDfNAjdX6/I7YKkpSxw9w=; h=From:To:Cc:Subject:Date:From; b=OjKbmQzqRpl9HpOMGUuOoBQi8ddI3ASuTf8v7AqCqFJvHgDLIGBFS0nBbauZd9cUM VxNbLsCW4qA/NonHqpNG8b48LPBvx9VXSh8/QMspP5UPzyti5mNgjL96Jj5pMphKo0 e2aDJCGnRMxD39tH/lyayEj4BwCo7YP9SAu+KQ8k= Received: from isaacm-linux.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: isaacm@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id D5848602FC; Tue, 20 Mar 2018 22:14:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521584067; bh=zvhu6sYoQC4hMm+uuPQ1DxbDfNAjdX6/I7YKkpSxw9w=; h=From:To:Cc:Subject:Date:From; b=OjKbmQzqRpl9HpOMGUuOoBQi8ddI3ASuTf8v7AqCqFJvHgDLIGBFS0nBbauZd9cUM VxNbLsCW4qA/NonHqpNG8b48LPBvx9VXSh8/QMspP5UPzyti5mNgjL96Jj5pMphKo0 e2aDJCGnRMxD39tH/lyayEj4BwCo7YP9SAu+KQ8k= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org D5848602FC Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=isaacm@codeaurora.org From: "Isaac J. Manjarres" To: catalin.marinas@arm.com, will.deacon@arm.com Subject: [PATCH] arm/arm64: smccc: Fix CLANG compilation for ARM 64 bit archs Date: Tue, 20 Mar 2018 15:14:06 -0700 Message-Id: <1521584046-19692-1-git-send-email-isaacm@codeaurora.org> X-Mailer: git-send-email 1.9.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180320_151439_055643_14915370 X-CRM114-Status: GOOD ( 10.57 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Isaac J. Manjarres" , tsoni@codeaurora.org, psodagud@codeaurora.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Currently, there are references to registers that have had their names changed in 64 bit ARM architectures, such as "r0." While GCC automatically does the conversion of these registers to their 64 bit counterparts, CLANG does not, resulting in compilation failures when building the kernel. Allow for differentiation of which register names to use, based on ARM architecture. Change-Id: If89d47b2feb217d97bb61a3f99e61096705a4984 Signed-off-by: Isaac J. Manjarres --- include/linux/arm-smccc.h | 57 ++++++++++++++++++++++++++++++----------------- 1 file changed, 37 insertions(+), 20 deletions(-) diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h index a031897..1208729 100644 --- a/include/linux/arm-smccc.h +++ b/include/linux/arm-smccc.h @@ -155,6 +155,15 @@ asmlinkage void __arm_smccc_hvc(unsigned long a0, unsigned long a1, #define SMCCC_SMC_INST "smc #0" #define SMCCC_HVC_INST "hvc #0" +#define R0_STR "x0" +#define R1_STR "x1" +#define R2_STR "x2" +#define R3_STR "x3" +#define R4_STR "x4" +#define R5_STR "x5" +#define R6_STR "x6" +#define R7_STR "x7" + #elif defined(CONFIG_ARM) #include @@ -162,6 +171,14 @@ asmlinkage void __arm_smccc_hvc(unsigned long a0, unsigned long a1, #define SMCCC_SMC_INST __SMC(0) #define SMCCC_HVC_INST __HVC(0) +#define R0_STR "r0" +#define R1_STR "r1" +#define R2_STR "r2" +#define R3_STR "r3" +#define R4_STR "r4" +#define R5_STR "r5" +#define R6_STR "r6" +#define R7_STR "r7" #endif @@ -194,47 +211,47 @@ asmlinkage void __arm_smccc_hvc(unsigned long a0, unsigned long a1, #define __declare_arg_0(a0, res) \ struct arm_smccc_res *___res = res; \ - register u32 r0 asm("r0") = a0; \ - register unsigned long r1 asm("r1"); \ - register unsigned long r2 asm("r2"); \ - register unsigned long r3 asm("r3") + register u32 r0 asm(R0_STR) = a0; \ + register unsigned long r1 asm(R1_STR); \ + register unsigned long r2 asm(R2_STR); \ + register unsigned long r3 asm(R3_STR) #define __declare_arg_1(a0, a1, res) \ struct arm_smccc_res *___res = res; \ - register u32 r0 asm("r0") = a0; \ - register typeof(a1) r1 asm("r1") = a1; \ - register unsigned long r2 asm("r2"); \ - register unsigned long r3 asm("r3") + register u32 r0 asm(R0_STR) = a0; \ + register typeof(a1) r1 asm(R1_STR) = a1; \ + register unsigned long r2 asm(R2_STR); \ + register unsigned long r3 asm(R3_STR) #define __declare_arg_2(a0, a1, a2, res) \ struct arm_smccc_res *___res = res; \ - register u32 r0 asm("r0") = a0; \ - register typeof(a1) r1 asm("r1") = a1; \ - register typeof(a2) r2 asm("r2") = a2; \ - register unsigned long r3 asm("r3") + register u32 r0 asm(R0_STR) = a0; \ + register typeof(a1) r1 asm(R1_STR) = a1; \ + register typeof(a2) r2 asm(R2_STR) = a2; \ + register unsigned long r3 asm(R3_STR) #define __declare_arg_3(a0, a1, a2, a3, res) \ struct arm_smccc_res *___res = res; \ - register u32 r0 asm("r0") = a0; \ - register typeof(a1) r1 asm("r1") = a1; \ - register typeof(a2) r2 asm("r2") = a2; \ - register typeof(a3) r3 asm("r3") = a3 + register u32 r0 asm(R0_STR) = a0; \ + register typeof(a1) r1 asm(R1_STR) = a1; \ + register typeof(a2) r2 asm(R2_STR) = a2; \ + register typeof(a3) r3 asm(R3_STR) = a3 #define __declare_arg_4(a0, a1, a2, a3, a4, res) \ __declare_arg_3(a0, a1, a2, a3, res); \ - register typeof(a4) r4 asm("r4") = a4 + register typeof(a4) r4 asm(R4_STR) = a4 #define __declare_arg_5(a0, a1, a2, a3, a4, a5, res) \ __declare_arg_4(a0, a1, a2, a3, a4, res); \ - register typeof(a5) r5 asm("r5") = a5 + register typeof(a5) r5 asm(R5_STR) = a5 #define __declare_arg_6(a0, a1, a2, a3, a4, a5, a6, res) \ __declare_arg_5(a0, a1, a2, a3, a4, a5, res); \ - register typeof(a6) r6 asm("r6") = a6 + register typeof(a6) r6 asm(R6_STR) = a6 #define __declare_arg_7(a0, a1, a2, a3, a4, a5, a6, a7, res) \ __declare_arg_6(a0, a1, a2, a3, a4, a5, a6, res); \ - register typeof(a7) r7 asm("r7") = a7 + register typeof(a7) r7 asm(R7_STR) = a7 #define ___declare_args(count, ...) __declare_arg_ ## count(__VA_ARGS__) #define __declare_args(count, ...) ___declare_args(count, __VA_ARGS__)