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Wed, 21 Mar 2018 18:56:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521658585; bh=+bI0tm8bhHIDFysh3wegWVamtyhDD/7eP9KsoC1eST4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ENdnE0fCmFZFjAkM0ZUZZ8ZoTXek0KCPaVsvOrl3FSBWEV27vaoRgsm6k+fyC7tfU jKZbSIdufKsmHhIXFGFsrc+6BqxteS1vS6ko/VRC013A1m2yzOlXBwL6ifu3Ppi0Gg 7T0nXmc/9Qy2FUoIPUa2uzGukqeZf+Owq0inWnHg= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 487FB60817 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=okaya@codeaurora.org From: Sinan Kaya To: jeffrey.t.kirsher@intel.com Subject: [PATCH REPOST v4 4/7] igb: eliminate duplicate barriers on weakly-ordered archs Date: Wed, 21 Mar 2018 14:56:08 -0400 Message-Id: <1521658572-26354-5-git-send-email-okaya@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1521658572-26354-1-git-send-email-okaya@codeaurora.org> References: <1521658572-26354-1-git-send-email-okaya@codeaurora.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180321_115631_047831_6294FCA5 X-CRM114-Status: GOOD ( 12.24 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sulrich@codeaurora.org, netdev@vger.kernel.org, timur@codeaurora.org, linux-kernel@vger.kernel.org, Sinan Kaya , intel-wired-lan@lists.osuosl.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Code includes wmb() followed by writel(). writel() already has a barrier on some architectures like arm64. This ends up CPU observing two barriers back to back before executing the register write. Since code already has an explicit barrier call, changing writel() to writel_relaxed(). Signed-off-by: Sinan Kaya Reviewed-by: Alexander Duyck --- drivers/net/ethernet/intel/igb/igb_main.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/intel/igb/igb_main.c b/drivers/net/ethernet/intel/igb/igb_main.c index b88fae7..82aea92 100644 --- a/drivers/net/ethernet/intel/igb/igb_main.c +++ b/drivers/net/ethernet/intel/igb/igb_main.c @@ -5671,7 +5671,7 @@ static int igb_tx_map(struct igb_ring *tx_ring, igb_maybe_stop_tx(tx_ring, DESC_NEEDED); if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) { - writel(i, tx_ring->tail); + writel_relaxed(i, tx_ring->tail); /* we need this if more than one processor can write to our tail * at a time, it synchronizes IO on IA64/Altix systems @@ -8072,7 +8072,7 @@ void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) * such as IA-64). */ wmb(); - writel(i, rx_ring->tail); + writel_relaxed(i, rx_ring->tail); } }