From patchwork Thu Mar 22 20:50:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Isaac J. Manjarres" X-Patchwork-Id: 10302301 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 55D5260386 for ; Thu, 22 Mar 2018 20:51:13 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 452242899C for ; Thu, 22 Mar 2018 20:51:13 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 37F97289B7; Thu, 22 Mar 2018 20:51:13 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id BDDF62899C for ; Thu, 22 Mar 2018 20:51:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To: References:List-Owner; bh=qQEimf3yVISZInCWoewRO+1Qn5Ke2PTA/eRAh+p5Gpk=; b=eqD 4NAFCI3FtBVKhJSj3UzbON8GLypnIwXDWZ/NEMeAwA/ekWU7ryadH8LVN0b2IpKYh0j0JMAvdzrMO TWHpbsNp8Nz2eGzZE3VV9Sa50vuqQcRkmcVCjTshVeAsFk5u+nqeJ/HzeTXvhS9r4flVjqkH5YXg7 uw1Nf3Owjywb8qZlMeBYsF53W9pAOZBtXFMACDuyATKuE4fps5RdjgnDc1788xezszNSg1LacklQ8 bBTtDiQ6yXENTOCSJOpAveZYe5ndO0AHaopZDGBLoqkhXvG0NaVwJJBJQhMwCFRML4CoOGd+rDAjf wjlQLkTI6lwH8KS+6hIwSvsv1pgvpTA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1ez7Ax-0001Q7-L4; Thu, 22 Mar 2018 20:51:07 +0000 Received: from smtp.codeaurora.org ([198.145.29.96]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1ez7At-0001Ns-SM for linux-arm-kernel@lists.infradead.org; Thu, 22 Mar 2018 20:51:05 +0000 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id F2A5060C54; Thu, 22 Mar 2018 20:50:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521751853; bh=cOVfUUEzBzQ8KcRO2sHGp41x2fbpvHrDLAOd/S7POeU=; h=From:To:Cc:Subject:Date:From; b=loLcT+LGNi1ICy91ZzwIBIUYDZUGTU/YSBYmWFNWg7hovDLbpccr6WcxGB8S0Nqx6 ZdOfdspWtBB3UxVUgKatTLWspQtuJ4wp5iSG/2XnI6MmeuAeNygZNKfHI2IHoSNCyi 6KPee21+dtMkMF/drZpTfWw9eLdbLFxG+gaSM3p8= Received: from isaacm-linux.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: isaacm@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id DFE9B6055D; Thu, 22 Mar 2018 20:50:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521751852; bh=cOVfUUEzBzQ8KcRO2sHGp41x2fbpvHrDLAOd/S7POeU=; h=From:To:Cc:Subject:Date:From; b=NBIFRyhh79Y14aGU3vbqtwfwyb+A2Y67qeMugGAwohqd9njybzzu/f/BsbyRlDkn3 PpAfZ9eJNFQnZSTV4cTl6S8ukia4Bm6BEf/mteRLIKNmfQDQf3qFWX7m6jvOFjlZk1 zNIW2kQPoQjU3AlEMgtI4CwIdiNINPRPtPZ+gEzE= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org DFE9B6055D Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=isaacm@codeaurora.org From: "Isaac J. Manjarres" To: catalin.marinas@arm.com, will.deacon@arm.com Subject: [PATCH v2] arm/arm64: smccc: Fix CLANG compilation for arm64 Date: Thu, 22 Mar 2018 13:50:38 -0700 Message-Id: <1521751838-18912-1-git-send-email-isaacm@codeaurora.org> X-Mailer: git-send-email 1.9.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180322_135103_967544_9A05182E X-CRM114-Status: GOOD ( 11.48 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Isaac J. Manjarres" , tsoni@codeaurora.org, marc.zyngier@arm.com, mark.rutland@arm.com, psodagud@codeaurora.org, robin.murphy@arm.com, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP When CLANG compiles inline assembly for 64 bit ARM architectures, it is unable to map register names, such as "r0" to the correct alias, such as "x0" for 64 bit accesses, and "w0" for 32 bit accesses. While GCC can perform this mapping, CLANG can not, which results in compilation failures when building the kernel. Allow for differentiation of which register names to use, based on ARM architecture, to compile the kernel with CLANG. Signed-off-by: Isaac J. Manjarres --- include/linux/arm-smccc.h | 43 +++++++++++++++++++++++-------------------- 1 file changed, 23 insertions(+), 20 deletions(-) diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h index a031897..0f2846e 100644 --- a/include/linux/arm-smccc.h +++ b/include/linux/arm-smccc.h @@ -155,6 +155,8 @@ asmlinkage void __arm_smccc_hvc(unsigned long a0, unsigned long a1, #define SMCCC_SMC_INST "smc #0" #define SMCCC_HVC_INST "hvc #0" +#define SMCCC_REG(n) "x" #n + #elif defined(CONFIG_ARM) #include @@ -162,6 +164,7 @@ asmlinkage void __arm_smccc_hvc(unsigned long a0, unsigned long a1, #define SMCCC_SMC_INST __SMC(0) #define SMCCC_HVC_INST __HVC(0) +#define SMCCC_REG(n) "r" #n #endif @@ -194,47 +197,47 @@ asmlinkage void __arm_smccc_hvc(unsigned long a0, unsigned long a1, #define __declare_arg_0(a0, res) \ struct arm_smccc_res *___res = res; \ - register u32 r0 asm("r0") = a0; \ - register unsigned long r1 asm("r1"); \ - register unsigned long r2 asm("r2"); \ - register unsigned long r3 asm("r3") + register u32 r0 asm(SMCCC_REG(0)) = a0; \ + register unsigned long r1 asm(SMCCC_REG(1)); \ + register unsigned long r2 asm(SMCCC_REG(2)); \ + register unsigned long r3 asm(SMCCC_REG(3)) #define __declare_arg_1(a0, a1, res) \ struct arm_smccc_res *___res = res; \ - register u32 r0 asm("r0") = a0; \ - register typeof(a1) r1 asm("r1") = a1; \ - register unsigned long r2 asm("r2"); \ - register unsigned long r3 asm("r3") + register u32 r0 asm(SMCCC_REG(0)) = a0; \ + register typeof(a1) r1 asm(SMCCC_REG(1)) = a1; \ + register unsigned long r2 asm(SMCCC_REG(2)); \ + register unsigned long r3 asm(SMCCC_REG(3)) #define __declare_arg_2(a0, a1, a2, res) \ struct arm_smccc_res *___res = res; \ - register u32 r0 asm("r0") = a0; \ - register typeof(a1) r1 asm("r1") = a1; \ - register typeof(a2) r2 asm("r2") = a2; \ - register unsigned long r3 asm("r3") + register u32 r0 asm(SMCCC_REG(0)) = a0; \ + register typeof(a1) r1 asm(SMCCC_REG(1)) = a1; \ + register typeof(a2) r2 asm(SMCCC_REG(2)) = a2; \ + register unsigned long r3 asm(SMCCC_REG(3)) #define __declare_arg_3(a0, a1, a2, a3, res) \ struct arm_smccc_res *___res = res; \ - register u32 r0 asm("r0") = a0; \ - register typeof(a1) r1 asm("r1") = a1; \ - register typeof(a2) r2 asm("r2") = a2; \ - register typeof(a3) r3 asm("r3") = a3 + register u32 r0 asm(SMCCC_REG(0)) = a0; \ + register typeof(a1) r1 asm(SMCCC_REG(1)) = a1; \ + register typeof(a2) r2 asm(SMCCC_REG(2)) = a2; \ + register typeof(a3) r3 asm(SMCCC_REG(3)) = a3 #define __declare_arg_4(a0, a1, a2, a3, a4, res) \ __declare_arg_3(a0, a1, a2, a3, res); \ - register typeof(a4) r4 asm("r4") = a4 + register typeof(a4) r4 asm(SMCCC_REG(4)) = a4 #define __declare_arg_5(a0, a1, a2, a3, a4, a5, res) \ __declare_arg_4(a0, a1, a2, a3, a4, res); \ - register typeof(a5) r5 asm("r5") = a5 + register typeof(a5) r5 asm(SMCCC_REG(5)) = a5 #define __declare_arg_6(a0, a1, a2, a3, a4, a5, a6, res) \ __declare_arg_5(a0, a1, a2, a3, a4, a5, res); \ - register typeof(a6) r6 asm("r6") = a6 + register typeof(a6) r6 asm(SMCCC_REG(6)) = a6 #define __declare_arg_7(a0, a1, a2, a3, a4, a5, a6, a7, res) \ __declare_arg_6(a0, a1, a2, a3, a4, a5, a6, res); \ - register typeof(a7) r7 asm("r7") = a7 + register typeof(a7) r7 asm(SMCCC_REG(7)) = a7 #define ___declare_args(count, ...) __declare_arg_ ## count(__VA_ARGS__) #define __declare_args(count, ...) ___declare_args(count, __VA_ARGS__)