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Fri, 23 Mar 2018 18:21:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521829286; bh=f1ihlSnXBrZwZ+tQTbq2kIBF0Y4Q2cHJM3mN7WKo6u8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=abRl+YAt9wMZB/CXMDWazms/zY3mvsjE9+u4PvaXJKHXThbN9Kxe1q1PJtP7npeC/ wRHHf1FKjc1wRQnEK2InCfx9li8pLyAYWOD45bNjpVhHFQ6gaO4ePEFw4wuFFkssxw mlqwE2gCDaO6d4joUTvG2dpmMkvIBHtStx4Gg3Vg= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 357E76030F Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=okaya@codeaurora.org From: Sinan Kaya To: jeffrey.t.kirsher@intel.com Subject: [PATCH v6 1/7] i40e/i40evf: Eliminate duplicate barriers on weakly-ordered archs Date: Fri, 23 Mar 2018 14:21:11 -0400 Message-Id: <1521829277-9398-2-git-send-email-okaya@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1521829277-9398-1-git-send-email-okaya@codeaurora.org> References: <1521829277-9398-1-git-send-email-okaya@codeaurora.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180323_112136_226031_7CAA467D X-CRM114-Status: GOOD ( 12.71 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sulrich@codeaurora.org, netdev@vger.kernel.org, timur@codeaurora.org, linux-kernel@vger.kernel.org, Sinan Kaya , intel-wired-lan@lists.osuosl.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Code includes wmb() followed by writel(). writel() already has a barrier on some architectures like arm64. This ends up CPU observing two barriers back to back before executing the register write. Since code already has an explicit barrier call, changing writel() to writel_relaxed(). Signed-off-by: Sinan Kaya --- drivers/net/ethernet/intel/i40e/i40e_txrx.c | 24 ++++++++++++++++++++---- drivers/net/ethernet/intel/i40evf/i40e_txrx.c | 9 +++++++-- 2 files changed, 27 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/intel/i40e/i40e_txrx.c b/drivers/net/ethernet/intel/i40e/i40e_txrx.c index c6972bd..fc10cc0 100644 --- a/drivers/net/ethernet/intel/i40e/i40e_txrx.c +++ b/drivers/net/ethernet/intel/i40e/i40e_txrx.c @@ -186,7 +186,13 @@ static int i40e_program_fdir_filter(struct i40e_fdir_filter *fdir_data, /* Mark the data descriptor to be watched */ first->next_to_watch = tx_desc; - writel(tx_ring->next_to_use, tx_ring->tail); + writel_relaxed(tx_ring->next_to_use, tx_ring->tail); + + /* We need this if more than one processor can write to our tail + * at a time, it synchronizes IO on IA64/Altix systems + */ + mmiowb(); + return 0; dma_fail: @@ -1529,7 +1535,12 @@ static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val) * such as IA-64). */ wmb(); - writel(val, rx_ring->tail); + writel_relaxed(val, rx_ring->tail); + + /* We need this if more than one processor can write to our tail + * at a time, it synchronizes IO on IA64/Altix systems + */ + mmiowb(); } /** @@ -2412,7 +2423,12 @@ static int i40e_clean_rx_irq(struct i40e_ring *rx_ring, int budget) */ wmb(); - writel(xdp_ring->next_to_use, xdp_ring->tail); + writel_relaxed(xdp_ring->next_to_use, xdp_ring->tail); + + /* We need this if more than one processor can write to our tail + * at a time, it synchronizes IO on IA64/Altix systems + */ + mmiowb(); } rx_ring->skb = skb; @@ -3437,7 +3453,7 @@ static inline int i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb, /* notify HW of packet */ if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) { - writel(i, tx_ring->tail); + writel_relaxed(i, tx_ring->tail); /* we need this if more than one processor can write to our tail * at a time, it synchronizes IO on IA64/Altix systems diff --git a/drivers/net/ethernet/intel/i40evf/i40e_txrx.c b/drivers/net/ethernet/intel/i40evf/i40e_txrx.c index 1ae112f..ca02762 100644 --- a/drivers/net/ethernet/intel/i40evf/i40e_txrx.c +++ b/drivers/net/ethernet/intel/i40evf/i40e_txrx.c @@ -810,7 +810,12 @@ static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val) * such as IA-64). */ wmb(); - writel(val, rx_ring->tail); + writel_relaxed(val, rx_ring->tail); + + /* We need this if more than one processor can write to our tail + * at a time, it synchronizes IO on IA64/Altix systems + */ + mmiowb(); } /** @@ -2379,7 +2384,7 @@ static inline void i40evf_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb, /* notify HW of packet */ if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) { - writel(i, tx_ring->tail); + writel_relaxed(i, tx_ring->tail); /* we need this if more than one processor can write to our tail * at a time, it synchronizes IO on IA64/Altix systems