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Fri, 23 Mar 2018 18:53:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521831188; bh=7tRk2PQjvYjISXUp3trZXXD1JU8IQFheC8Ye8TjPFrs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Hr+AvUXRkt2MaSr8OhsHxEJrjgiodMJREASl4PLhIJ3rCR2HYcOnBe27lzt92XWbX d6o0d2j8BPb4sKKfwlAsIiYgVv5PBkQbMhjs41OIj24T+Xhyx2vyNm4GzY4wsHMJRs WOBsWNkbm0i+0Yu3jp985CY2CC7czvWOQTIxPGYI= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 11FD960F61 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=okaya@codeaurora.org From: Sinan Kaya To: jeffrey.t.kirsher@intel.com Subject: [PATCH v7 3/7] igbvf: eliminate duplicate barriers on weakly-ordered archs Date: Fri, 23 Mar 2018 14:52:56 -0400 Message-Id: <1521831180-25014-4-git-send-email-okaya@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1521831180-25014-1-git-send-email-okaya@codeaurora.org> References: <1521831180-25014-1-git-send-email-okaya@codeaurora.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180323_115315_227443_8763D36F X-CRM114-Status: GOOD ( 12.03 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sulrich@codeaurora.org, netdev@vger.kernel.org, timur@codeaurora.org, linux-kernel@vger.kernel.org, Sinan Kaya , intel-wired-lan@lists.osuosl.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Code includes wmb() followed by writel(). writel() already has a barrier on some architectures like arm64. This ends up CPU observing two barriers back to back before executing the register write. Since code already has an explicit barrier call, changing writel() to writel_relaxed(). Signed-off-by: Sinan Kaya --- drivers/net/ethernet/intel/igbvf/netdev.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/intel/igbvf/netdev.c b/drivers/net/ethernet/intel/igbvf/netdev.c index fa07876..df2283b 100644 --- a/drivers/net/ethernet/intel/igbvf/netdev.c +++ b/drivers/net/ethernet/intel/igbvf/netdev.c @@ -252,7 +252,7 @@ static void igbvf_alloc_rx_buffers(struct igbvf_ring *rx_ring, * such as IA-64). */ wmb(); - writel(i, adapter->hw.hw_addr + rx_ring->tail); + writel_relaxed(i, adapter->hw.hw_addr + rx_ring->tail); } } @@ -2298,7 +2298,7 @@ static inline void igbvf_tx_queue_adv(struct igbvf_adapter *adapter, tx_ring->buffer_info[first].next_to_watch = tx_desc; tx_ring->next_to_use = i; - writel(i, adapter->hw.hw_addr + tx_ring->tail); + writel_relaxed(i, adapter->hw.hw_addr + tx_ring->tail); /* we need this if more than one processor can write to our tail * at a time, it synchronizes IO on IA64/Altix systems */