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Tue, 27 Mar 2018 13:25:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1522157137; bh=NAEp+V9NzyNE2wZcjRscs8/TJjwtlXLqeanXNUYygek=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=DvICk5QGBssCWt+1fGYt0fCB80VYvytvtyhhMRbdnSzyBbiXCgWlE5I5aXnB5vMAO /wywNZG3xp76CtKD7mBf6ihs06wSMJZ/rOTX+7eWnW9a3VzSJgim0fTw87FJiMWlIy Jo3s04tDDU4Bs6DSfmuqfbLjPSAfS9VkGkT70/HU= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 6FA3160FAA Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=cpandya@codeaurora.org From: Chintan Pandya To: catalin.marinas@arm.com, will.deacon@arm.com, mark.rutland@arm.com, toshi.kani@hpe.com Subject: [PATCH v5 3/4] arm64: Implement page table free interfaces Date: Tue, 27 Mar 2018 18:54:59 +0530 Message-Id: <1522157100-16879-4-git-send-email-cpandya@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1522157100-16879-1-git-send-email-cpandya@codeaurora.org> References: <1522157100-16879-1-git-send-email-cpandya@codeaurora.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180327_062543_027368_F59FA9FB X-CRM114-Status: GOOD ( 13.06 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arch@vger.kernel.org, arnd@arndb.de, ard.biesheuvel@linaro.org, marc.zyngier@arm.com, gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org, kristina.martsenko@arm.com, takahiro.akashi@linaro.org, james.morse@arm.com, Chintan Pandya , tglx@linutronix.de, akpm@linux-foundation.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Implement pud_free_pmd_page() and pmd_free_pte_page(). Implementation requires, 1) Freeing of the un-used next level page tables 2) Clearing off the current pud/pmd entry 3) Invalidate TLB which could have previously valid but not stale entry Signed-off-by: Chintan Pandya --- V4->V5: - Using __flush_tlb_kernel_pgtable instead of flush_tlb_kernel_range arch/arm64/mm/mmu.c | 33 +++++++++++++++++++++++++++++++-- 1 file changed, 31 insertions(+), 2 deletions(-) diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c index da98828..3552c7a 100644 --- a/arch/arm64/mm/mmu.c +++ b/arch/arm64/mm/mmu.c @@ -45,6 +45,7 @@ #include #include #include +#include #define NO_BLOCK_MAPPINGS BIT(0) #define NO_CONT_MAPPINGS BIT(1) @@ -973,12 +974,40 @@ int pmd_clear_huge(pmd_t *pmdp) return 1; } +static int __pmd_free_pte_page(pmd_t *pmd, unsigned long addr, bool tlb_inv) +{ + pmd_t *table; + + if (pmd_val(*pmd)) { + table = __va(pmd_val(*pmd)); + pmd_clear(pmd); + if (tlb_inv) + __flush_tlb_kernel_pgtable(addr); + + free_page((unsigned long) table); + } + return 1; +} + int pud_free_pmd_page(pud_t *pud, unsigned long addr) { - return pud_none(*pud); + pmd_t *table; + int i; + + if (pud_val(*pud)) { + table = __va(pud_val(*pud)); + for (i = 0; i < PTRS_PER_PMD; i++) + __pmd_free_pte_page(&table[i], addr + (i * PMD_SIZE), + false); + + pud_clear(pud); + flush_tlb_kernel_range(addr, addr + PUD_SIZE); + free_page((unsigned long) table); + } + return 1; } int pmd_free_pte_page(pmd_t *pmd, unsigned long addr) { - return pmd_none(*pmd); + return __pmd_free_pte_page(pmd, addr, true); }