From patchwork Wed Mar 28 01:55:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philip Elcan X-Patchwork-Id: 10311997 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 0221960212 for ; Wed, 28 Mar 2018 01:56:00 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E704B29E2B for ; Wed, 28 Mar 2018 01:55:59 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D85EB29E35; Wed, 28 Mar 2018 01:55:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 6457029E2B for ; Wed, 28 Mar 2018 01:55:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To: References:List-Owner; bh=E92e+E02YsRowYHW/0m5rqcAgpn5IlbLut0PYej9CwY=; b=PrJ Y6AwaH1S+wkopzS042qhHI6Gq9DhQefr2Q0Zu+mRvukT99MdBtPqa2Z0+mw/gPiO3eGuLjkyL6mkV LZn1YfpEtLZDRMXnqZqugT4gmIzfeiaR7MofosJWeOJw67oce4Btu8lz8m44adT7+cbH6SqKfnlR+ Q1b4VOz+4ucbLHzsf8Ae5XFGwpJMK0fdyYNomqNO6gnhoQolawlpYa+Ol6iV0ranIIl7HSFF8Dqk3 0sOJRe4THBtGSX0MrHXZLIOViP3Z9nY/W47T7E8N86pHHfdaRX9ue1RKZ5fgnd6JbZ1kS4kmBEW/c LX8nEzuLqjcr5RDI5as8/R/QZbjQw+w==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1f10Ja-0005uK-CN; Wed, 28 Mar 2018 01:55:50 +0000 Received: from smtp.codeaurora.org ([198.145.29.96]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1f10JX-0005sL-MA for linux-arm-kernel@lists.infradead.org; Wed, 28 Mar 2018 01:55:49 +0000 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 2FE81607E4; Wed, 28 Mar 2018 01:55:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1522202137; bh=FXF7dMB24cXsedTlTW8t/b2khKzIi9pzG1la493PP7w=; h=From:To:Cc:Subject:Date:From; b=ZKZxA5YqwV/KNOG7zbi58136AhJs/Ma4EQbBTaKok3FmOCovtSWdbvvSI3SyK5pnF VKIbVvuAsh5ZnBelBonVeiY0yv+PuJyiz2tlcMknC+TU8lC+3gZE0jiPCNgjJAEioW T8ZebK8I1obLlxo98tb/oEld2PjW+yF7egPDI4Jo= Received: from krakatau.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: pelcan@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id ED7BA601EA; Wed, 28 Mar 2018 01:55:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1522202136; bh=FXF7dMB24cXsedTlTW8t/b2khKzIi9pzG1la493PP7w=; h=From:To:Cc:Subject:Date:From; b=nqSExfelekrc0N4jS5nPR7Paukn8xWVsyRAXo5vCpB3gDg16Wj5gTpK+b9Zheyrn3 QkWOmB1LFqGPyFt0548sz5UbNBrzvgbEGhtqauuNWbgYMRcGxMzpLUoUJ+2Q4OkF8W 7Bg/pJ3saDLIfGREY+zoNGVcYpGt277jyC4lNIg0= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org ED7BA601EA Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=pelcan@codeaurora.org From: Philip Elcan To: linux-arm-kernel@lists.infradead.org, Catalin Marinas , Will Deacon , Mark Rutland , Robin Murphy , linux-kernel@vger.kernel.org Subject: [PATCH V3] arm64: tlbflush: avoid writing RES0 bits Date: Tue, 27 Mar 2018 21:55:32 -0400 Message-Id: <1522202132-16998-1-git-send-email-pelcan@codeaurora.org> X-Mailer: git-send-email 1.9.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180327_185547_761518_A6D96085 X-CRM114-Status: GOOD ( 12.39 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Speier , Shanker Donthineni MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Several of the bits of the TLBI register operand are RES0 per the ARM ARM, so TLBI operations should avoid writing non-zero values to these bits. This patch adds a macro __TLBI_VADDR(addr, asid) that creates the operand register in the correct format and honors the RES0 bits. Signed-off-by: Philip Elcan Acked-by: Mark Rutland --- arch/arm64/include/asm/tlbflush.h | 25 +++++++++++++++++-------- 1 file changed, 17 insertions(+), 8 deletions(-) diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h index 9e82dd7..dfc61d7 100644 --- a/arch/arm64/include/asm/tlbflush.h +++ b/arch/arm64/include/asm/tlbflush.h @@ -60,6 +60,15 @@ __tlbi(op, (arg) | USER_ASID_FLAG); \ } while (0) +/* This macro creates a properly formatted VA operand for the TLBI */ +#define __TLBI_VADDR(addr, asid) \ + ({ \ + unsigned long __ta = (addr) >> 12; \ + __ta &= GENMASK_ULL(43, 0); \ + __ta |= (unsigned long)(asid) << 48; \ + __ta; \ + }) + /* * TLB Management * ============== @@ -117,7 +126,7 @@ static inline void flush_tlb_all(void) static inline void flush_tlb_mm(struct mm_struct *mm) { - unsigned long asid = ASID(mm) << 48; + unsigned long asid = __TLBI_VADDR(0, ASID(mm)); dsb(ishst); __tlbi(aside1is, asid); @@ -128,7 +137,7 @@ static inline void flush_tlb_mm(struct mm_struct *mm) static inline void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr) { - unsigned long addr = uaddr >> 12 | (ASID(vma->vm_mm) << 48); + unsigned long addr = __TLBI_VADDR(uaddr, ASID(vma->vm_mm)); dsb(ishst); __tlbi(vale1is, addr); @@ -146,7 +155,7 @@ static inline void __flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end, bool last_level) { - unsigned long asid = ASID(vma->vm_mm) << 48; + unsigned long asid = ASID(vma->vm_mm); unsigned long addr; if ((end - start) > MAX_TLB_RANGE) { @@ -154,8 +163,8 @@ static inline void __flush_tlb_range(struct vm_area_struct *vma, return; } - start = asid | (start >> 12); - end = asid | (end >> 12); + start = __TLBI_VADDR(start, asid); + end = __TLBI_VADDR(end, asid); dsb(ishst); for (addr = start; addr < end; addr += 1 << (PAGE_SHIFT - 12)) { @@ -185,8 +194,8 @@ static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end return; } - start >>= 12; - end >>= 12; + start = __TLBI_VADDR(start, 0); + end = __TLBI_VADDR(end, 0); dsb(ishst); for (addr = start; addr < end; addr += 1 << (PAGE_SHIFT - 12)) @@ -202,7 +211,7 @@ static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end static inline void __flush_tlb_pgtable(struct mm_struct *mm, unsigned long uaddr) { - unsigned long addr = uaddr >> 12 | (ASID(mm) << 48); + unsigned long addr = __TLBI_VADDR(uaddr, ASID(mm)); __tlbi(vae1is, addr); __tlbi_user(vae1is, addr);