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Mon, 2 Apr 2018 19:06:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1522696003; bh=BdmRP6qJRGY4whJjtRjcHF3173APXkFebNUnK8CK/Hg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ef0LT/cnNnfvqAdn9dYIhHYJGWFb/nHj9LyTw0ndZzosEqUIChYKSY+yIRrKBhsyB ibAUMnORhDshXdS/bukwhcePlcjL5Hplnj0M+8+O5/+MGMymYVTt33lSHGg3l03KXQ ut3yQEXPwccpXDV66/R5q0KLPqjVueXoNxO+dnO4= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org E894060F6C Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=okaya@codeaurora.org From: Sinan Kaya To: jeffrey.t.kirsher@intel.com Subject: [PATCH v8 5/7] fm10k: Eliminate duplicate barriers on weakly-ordered archs Date: Mon, 2 Apr 2018 15:06:28 -0400 Message-Id: <1522695990-31082-6-git-send-email-okaya@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1522695990-31082-1-git-send-email-okaya@codeaurora.org> References: <1522695990-31082-1-git-send-email-okaya@codeaurora.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180402_120659_262810_E24AF309 X-CRM114-Status: GOOD ( 13.55 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sulrich@codeaurora.org, netdev@vger.kernel.org, timur@codeaurora.org, linux-kernel@vger.kernel.org, Sinan Kaya , intel-wired-lan@lists.osuosl.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP memory-barriers.txt has been updated as follows: "When using writel(), a prior wmb() is not needed to guarantee that the cache coherent memory writes have completed before writing to the MMIO region." Remove old IA-64 comments in the code along with unneeded wmb() in front of writel(). There are places in the code where wmb() has been used as a double barrier for CPU and IO in place of smp_wmb() and wmb() as an optimization. For such places, keep the wmb() but replace the following writel() with writel_relaxed() to have a sequence as wmb() writel_relaxed() mmio_wb() Signed-off-by: Sinan Kaya --- drivers/net/ethernet/intel/fm10k/fm10k_main.c | 15 ++------------- 1 file changed, 2 insertions(+), 13 deletions(-) diff --git a/drivers/net/ethernet/intel/fm10k/fm10k_main.c b/drivers/net/ethernet/intel/fm10k/fm10k_main.c index df86070..41e3aaa 100644 --- a/drivers/net/ethernet/intel/fm10k/fm10k_main.c +++ b/drivers/net/ethernet/intel/fm10k/fm10k_main.c @@ -172,13 +172,6 @@ void fm10k_alloc_rx_buffers(struct fm10k_ring *rx_ring, u16 cleaned_count) /* update next to alloc since we have filled the ring */ rx_ring->next_to_alloc = i; - /* Force memory writes to complete before letting h/w - * know there are new descriptors to fetch. (Only - * applicable for weak-ordered memory model archs, - * such as IA-64). - */ - wmb(); - /* notify hardware of new descriptors */ writel(i, rx_ring->tail); } @@ -1036,11 +1029,7 @@ static void fm10k_tx_map(struct fm10k_ring *tx_ring, /* record SW timestamp if HW timestamp is not available */ skb_tx_timestamp(first->skb); - /* Force memory writes to complete before letting h/w know there - * are new descriptors to fetch. (Only applicable for weak-ordered - * memory model archs, such as IA-64). - * - * We also need this memory barrier to make certain all of the + /* We need this memory barrier to make certain all of the * status bits have been updated before next_to_watch is written. */ wmb(); @@ -1055,7 +1044,7 @@ static void fm10k_tx_map(struct fm10k_ring *tx_ring, /* notify HW of packet */ if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) { - writel(i, tx_ring->tail); + writel_relaxed(i, tx_ring->tail); /* we need this if more than one processor can write to our tail * at a time, it synchronizes IO on IA64/Altix systems