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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arm-msm@vger.kernel.org, Helge Deller , Philippe Ombredanne , "James E.J. Bottomley" , linux-kernel@vger.kernel.org, Sinan Kaya , Greg Kroah-Hartman , Thomas Gleixner , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP parisc architecture seems to be mapping writeX() and writeX_relaxed() APIs to __raw_writeX() API. __raw_writeX() API doesn't provide any kind of ordering guarantees. commit 755bd04aaf4b ("io: define stronger ordering for the default writeX() implementation") changed asm-generic implementation to use a more conservative approach towards the writeX() API. Place a barrier() before the register write so that compiler doesn't optimize across the regiter operation. Signed-off-by: Sinan Kaya --- arch/parisc/include/asm/io.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/parisc/include/asm/io.h b/arch/parisc/include/asm/io.h index afe493b..2ec6405 100644 --- a/arch/parisc/include/asm/io.h +++ b/arch/parisc/include/asm/io.h @@ -196,18 +196,22 @@ static inline unsigned long long readq(const volatile void __iomem *addr) static inline void writeb(unsigned char b, volatile void __iomem *addr) { + barrier(); __raw_writeb(b, addr); } static inline void writew(unsigned short w, volatile void __iomem *addr) { + barrier(); __raw_writew((__u16 __force) cpu_to_le16(w), addr); } static inline void writel(unsigned int l, volatile void __iomem *addr) { + barrier(); __raw_writel((__u32 __force) cpu_to_le32(l), addr); } static inline void writeq(unsigned long long q, volatile void __iomem *addr) { + barrier(); __raw_writeq((__u64 __force) cpu_to_le64(q), addr); }